Patents by Inventor Chung-Hsiung Ho

Chung-Hsiung Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12133896
    Abstract: The present invention relates to a method for treating or alleviating an osteoporosis in a subject. The method comprises steps of identifying the subject having the osteoporosis, and administering to the subject an effective amount of a composition that increases a level of Discoidin Domain Receptor 1 (DDR1) protein in the subject.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: November 5, 2024
    Assignee: KAOHSIUNG MEDICAL UNIVERSITY
    Inventors: Chau-Zen Wang, Chung-Hwan Chen, Liang-Yin Chou, Yu Chou, Mei-Ling Ho, Yi-Hsiung Lin
  • Publication number: 20240355716
    Abstract: A die of the package device is covered by an encapsulation layer, a plurality of lead portions are configured on the bottom surface of the encapsulation layer, a side portion of each lead portion is also exposed on a side surface of the encapsulation layer, and thereby the package device is used as a side-wettable package device; wherein, in a process of manufacturing the package device, a conductive electroplated conducting layer is formed on the surface of the encapsulation layer, and the electroplated conducting layer is used to conduct electric power required during an electroplating process. After the electroplating process is completed, the electroplated conducting layer can be used as a heat dissipation layer for the package device. The heat dissipation layer completely covers the surface of the package device so as to increase heat dissipation area and to be attached by a heat sink.
    Type: Application
    Filed: June 30, 2023
    Publication date: October 24, 2024
    Inventors: CHUNG-HSIUNG HO, CHI-HSUEH LI, Yung-Hui WANG, WEN-LIANG HUANG
  • Publication number: 20240355703
    Abstract: The present invention provides a heat dissipative semiconductor package. The semiconductor package includes a package body in a flat rectangular shape. The semiconductor package further includes a die, a conductive block, multiple metal blocks, a molding layer, and a redistribution layer. A first contact of the die is electrically connected to a first pin. A second contact of the die is electrically connected to a second pin via the redistribution layer and the conductive block. The first pin and the second pin are respectively exposed from the bottom surface of the package body to curve, extend, and cover different side surfaces of the package body. The conductive block and the metal blocks are formed by dicing a same VCB. Heat generated by the die can be effectively dissipated externally through the first pin, the second pin, and the conductive block, and thus cooling the die.
    Type: Application
    Filed: June 14, 2023
    Publication date: October 24, 2024
    Inventors: CHUNG-HSIUNG HO, CHI-HSUEH LI, CHE FANG
  • Publication number: 20240310412
    Abstract: An universal probe card and a testing method are disclosed. The universal probe card includes a plurality of probes. The probes are configured to contact and test a plurality of different patterns to be tested. Each of the plurality of different patterns to be tested includes a plurality of portions to be tested. A pitch between the plurality of probes is a greatest common factor of pitches between the plurality of portions to be tested in the plurality of different patterns to be tested.
    Type: Application
    Filed: October 31, 2023
    Publication date: September 19, 2024
    Inventors: CHUNG-HSIUNG HO, CHIA-WEI CHEN, PING-JUI HSIEH
  • Publication number: 20240290668
    Abstract: A semiconductor device without resistance trimming pads has a device body, a fundamental resistor, and at least one trimming resistor. The device body has a surface with two testing pads and without resistance trimming pads. The fundamental resistor is formed in the device body. The at least one trimming resistor is formed in the device body and connected to the fundamental resistor in series between the two testing pads. Residuals of at least one fusible wire that has been fused are connected to the at least one trimming resistor.
    Type: Application
    Filed: April 11, 2023
    Publication date: August 29, 2024
    Inventors: CHUNG-HSIUNG HO, CHIA-WEI CHEN, SHAN-DE YANG
  • Publication number: 20240274484
    Abstract: A wafer-level-package device with peripheral side wall protection has a die, multiple conductive bumps, and a protection layer. The die has a top surface, a bottom surface, and a peripheral side wall. A cavity is formed on the peripheral side wall of the die and around the die. The multiple conductive bumps are mounted on at least one of the top surface and the bottom surface of the die. The protection layer covers the die, the cavity, and the multiple conductive bumps. The multiple conductive bumps are exposed from the protection layer.
    Type: Application
    Filed: March 7, 2023
    Publication date: August 15, 2024
    Inventors: CHUNG-HSIUNG HO, WEN-LIANG HUANG, JENG-SIAN WU
  • Publication number: 20240128185
    Abstract: A pre-forming adaptor for semiconductor packaging includes at least one lead frame and at least one packaging enclosure bonded with the at least one lead frame. Each of the lead frame and the packaging enclosure has a pre-forming shape provided according to a predetermined package outline of a semiconductor device.
    Type: Application
    Filed: December 12, 2022
    Publication date: April 18, 2024
    Inventors: Chung Hsiung Ho, Chi Hsueh Li
  • Publication number: 20240120241
    Abstract: The present invention provides an electrostatic charge detecting packaging device comprising a carrier, multiple dies, and multiple electrostatic-charge-sensitive components; the carrier has a surface; the dies are mounted on the surface of the carrier; and the electrostatic-charge-sensitive components are mounted on the surface of the carrier; since an electrostatic voltage tolerance of each of the electrostatic-charge-sensitive components is lower than an electrostatic voltage tolerance of each of the dies, accumulated electrostatic charges are more likely to discharge towards the electrostatic-charge-sensitive components than towards the dies, and as such, by electrically testing whether the electrostatic-charge-sensitive components are functioning normally when packaging the dies, the present invention allows personnel to debug for knowing which packaging steps exactly cause more serious problems that lead to damaging electrostatic discharges in the dies.
    Type: Application
    Filed: November 30, 2022
    Publication date: April 11, 2024
    Inventors: Chung-Hsiung HO, Chien-Chun Wang, Li-Qiang Ye, Chi-Hsueh Li
  • Publication number: 20240112943
    Abstract: A die suction assistance device is provided to a wafer. The wafer is diced into multiple dies, and a tape is taped on a bottom side of the wafer. The die suction assistance device includes a platform and multiple support structures mounted in the platform. Multiple air ducts are formed among adjacent support structures. When the wafer is air-tightly mounted on the platform, the wafer is supported by the support structures. When an external vacuum device vacuums air out of the platform, a vacuum environment with negative pressure is created in the air ducts. This allows the tape to partially separate from a backside of each of the dies towards the air ducts, and allows the dies to be picked up respectively by a suction nozzle with less chance of being damaged, securing integrities of dies.
    Type: Application
    Filed: November 8, 2022
    Publication date: April 4, 2024
    Applicant: PANJIT INTERNATIONAL INC.
    Inventors: Chung-Hsiung HO, Chi-Hsueh LI, Wen-Liang HUANG
  • Patent number: 11916030
    Abstract: A side wettable package includes a molding compound, a chip and multiple conductive pads exposed from a bottom surface of the molding compound. The conductive pads include peripheral conductive pads arranged near a side wall of the molding compound. Each of the peripheral conductive pads is over etched to form an undercut. When the side wettable package is connected to a circuit board via solder, the solder ascends to the undercut of the peripheral conductive pads for improving connection yield and facilitating inspection of soldering quality.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: February 27, 2024
    Assignee: PANJIT INTERNATIONAL INC.
    Inventors: Chung-Hsiung Ho, Chi-Hsueh Li
  • Publication number: 20240030155
    Abstract: The present invention provides a wafer level chip scale package (WLCSP) unit; the WLCSP unit includes a die, a dielectric layer, and a bottom metal layer; the die has a substrate and an active surface; multiple pads are mounted on the active surface, and a soldering layer is mounted on a surface of each of the pads; the dielectric layer covers an upper part of four lateral surfaces of the die, exposing a lower part of the four lateral surfaces of the die; the bottom metal layer is mounted on a bottom surface of the substrate; the bottom metal layer protects a bottom surface of the dies, dissipates heat generated by the dies, and also protects the dies from external electromagnetic interferences (EMI).
    Type: Application
    Filed: August 10, 2022
    Publication date: January 25, 2024
    Applicant: PANJIT INTERNATIONAL INC.
    Inventors: Chung-Hsiung HO, Chi-Hsueh LI, Yu-Ming HSU, Yung-Hui WANG, Chia-Wei CHEN
  • Patent number: 11848254
    Abstract: A semiconductor package includes a molding compound, a chip and a conductive pad, wherein the chip is electrically connected to the conductive pad and both are encapsulated in the molding compound. An anchor flange is formed around a top surface of the conductive pad by over plating. When the conductive pad is embedded in the molding compound, the anchor flange engages the molding compound to prevent the conductive pad from separation. Bottoms of a chip and the conductive pad are exposed from the molding compound for electrically soldering to a circuit board.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: December 19, 2023
    Assignee: Panjit International Inc.
    Inventors: Chung-Hsiung Ho, Chi-Hsueh Li
  • Publication number: 20230402515
    Abstract: A metal oxide semiconductor (MOS) with multiple drain vias includes a semiconductor substrate, which is divided into a gate region, a source region and a drain region. On the same surface of the semiconductor substrate in the gate region, a connection layer is formed in the source region and the drain region with a low-resistance metal material. A plurality of conductive elements, such as solder balls, can be directly arranged on the connection layer, so that the MOS can be soldered to the circuit board through the conductive elements distributed on the same surface. In the drain region, there are a plurality of vias. The inside of each via is filled with the connection layer and extends to the inside of the semiconductor substrate. With the aforementioned structure, the MOS has the advantage of low on-resistance RDS(ON).
    Type: Application
    Filed: October 17, 2022
    Publication date: December 14, 2023
    Inventors: CHUNG-HSIUNG HO, CHIH-HUNG CHANG, CHI-HSUEH LI
  • Publication number: 20230395465
    Abstract: A semiconductor package with improved solderability at sidewall includes a chip, a molding compound encapsulating the chip, and multiple leads distributed at sidewalls of the semiconductor package. The leads are formed as a conductive layer that is electrically connected to bonding pads of the chip. Each of the leads has a stepped surface exposed from the molding compound, wherein the stepped surface is shaped by two sequentially overlapped photoresist layers. The stepped surface of each lead allows to accommodate more solder to enhance the reliability of a solder joint between the semiconductor and a printed circuit board. Therefore, the solder joints of the semiconductor package are easily inspected by automatic optical inspection (AOI) equipment.
    Type: Application
    Filed: June 2, 2022
    Publication date: December 7, 2023
    Inventors: CHUNG-HSIUNG HO, WEI-MING HUNG, CHI-HSUEH LI, CHIEN-CHUN WANG, JENG-SIAN WU
  • Publication number: 20230395553
    Abstract: A package device preventing solder overflow provides a space or structure to limit the location of the solder when dispensing the solder. The package device includes a die, an anti-overflow layer, a first pin, a second pin, and a package body. The die has an electrode pad. The anti-overflow layer is disposed on a top surface of the electrode pad and has an opening to expose the top surface of the electrode pad. The first pin is connected to the die. The second pin is soldered to the electrode pad of the die through the opening of the anti-overflow layer. The package body covers the die.
    Type: Application
    Filed: June 29, 2022
    Publication date: December 7, 2023
    Inventors: CHUNG-HSIUNG HO, SHUN-CHI SHEN, CHI-HSUEH LI
  • Publication number: 20230395469
    Abstract: A thin semiconductor packaging unit includes a semiconductor die, a mold, two contact bulks, a first bridge layer, a second bride layer, and two insulation layers; the mold covers a side surface of the semiconductor die; the mold includes two sides, and each of the sides includes at least one first contact area; the two contact bulks are respectively mounted on the two sides of the mold; each of the contact bulks includes at least one second contact area connecting the at least one first contact area; the first bridge layer connects the top electrode of the semiconductor die to one of the contact bulks; the second bride layer connects the bottom electrode of the semiconductor die to the other one of the contact bulks; the two insulation layers respectively cover the first bridge layer and the second bridge layer; the present invention dissipates heat efficiently.
    Type: Application
    Filed: July 5, 2022
    Publication date: December 7, 2023
    Applicant: PANJIT INTERNATIONAL INC.
    Inventors: CHUNG-HSIUNG HO, CHI-HSUEH LI
  • Publication number: 20230326833
    Abstract: A method for manufacturing a packaged component with a composite pin structure has: dividing a substrate into a body area and a pin area, wherein a chip is arranged on the body area of the substrate and is electrically connected to conductive layers on the opposite surfaces of the substrate. The pin area is pre-defined with multiple parallel pin positions. After the electrical connection of the chip is completed in the body area, a cutting tool is used to cut along the peripheries of the body area and the pin positions to obtain a packaged component body and multiple pins. Each of the pins is integrally formed by the substrate of the packaged component body without using a conventional lead frame.
    Type: Application
    Filed: May 11, 2022
    Publication date: October 12, 2023
    Applicant: PANJIT INTERNATIONAL INC.
    Inventors: Yung-Hui WANG, CHUNG-HSIUNG HO, CHI-HSUEH LI
  • Patent number: 11664345
    Abstract: A semiconductor package element includes a die, a passive layer, a conductive structure and an encapsulation layer. The die includes a first surface, a second surface and a third surface. The second surface is opposite to the first surface. The third surface is connected between the first surface and the second surface. The passive layer is disposed on the first surface and formed with a hole. The conductive structure is electrically coupled to the die through the hole. The encapsulation layer covers the first surface and the third surface of the die, wherein the passive layer is embedded in the encapsulation layer, a portion of the conductive structure is embedded in the encapsulation layer, and the other portion of the conductive structure protrudes from an etched surface of the encapsulation layer, the etched surface is formed by plasma etching.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: May 30, 2023
    Assignee: PANJIT INTERNATIONAL INC.
    Inventors: Chung-Hsiung Ho, Chih-Hung Chang, Chi-Hsueh Li
  • Patent number: 11594425
    Abstract: A semiconductor package structure, including a lead frame, a die disposed on the front side of the lead frame, and a molding piece disposed on the lead frame and encapsulates the die, wherein the lead frame is provided with two extension portions extending respectively from two sides of the molding piece, and the extension portion is provided with recessed front surface and back surface on which a plating layer is formed.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: February 28, 2023
    Assignee: PANJIT INTERNATIONAL INC.
    Inventors: Chung-Hsiung Ho, Chi-Hsueh Li
  • Patent number: 11562947
    Abstract: A semiconductor package includes a molding compound, a chip and a conductive pad, wherein the chip is electrically connected to the conductive pad and both are encapsulated in the molding compound. An anchor flange is formed around a top surface of the conductive pad by over plating. When the conductive pad is embedded in the molding compound, the anchor flange engages the molding compound to prevent the conductive pad from separation. Bottoms of a chip and the conductive pad are exposed from the molding compound for electrically soldering to a circuit board.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: January 24, 2023
    Assignee: Panjit International Inc.
    Inventors: Chung-Hsiung Ho, Chi-Hsueh Li