Patents by Inventor Chung-Hsiung Wang

Chung-Hsiung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210028108
    Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.
    Type: Application
    Filed: October 8, 2020
    Publication date: January 28, 2021
    Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
  • Publication number: 20200365712
    Abstract: Various transistors, such as horizontal gate-all-around transistors, and methods of fabricating such are disclosed herein. An exemplary transistor includes a first nanowire and a second nanowire that include a first semiconductor material, a gate that wraps a channel region of the first nanowire and the second nanowire, and source/drain feature that wraps source/drain regions of the first nanowire and the second nanowire. The source/drain feature includes a second semiconductor material that is configured differently than the first semiconductor material. In some implementations, the transistor further includes a fin-like semiconductor layer disposed over a substrate. The first nanowire and the second nanowire are disposed over the fin-like semiconductor layer, such that the first nanowire, the second nanowire, and the fin-like semiconductor layer extend substantially parallel to one another along the same length-wise direction.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 19, 2020
    Inventors: Chun-Hsiung Lin, Chung-Cheng Wu, Carlos H. Diaz, Chih-Hao Wang, Wen-Hsing Hsieh, Yi-Ming Sheu
  • Patent number: 10804200
    Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
  • Patent number: 10734500
    Abstract: Various transistors, such as horizontal gate-all-around transistors, and methods of fabricating such are disclosed herein. An exemplary transistor includes a first nanowire and a second nanowire that include a first semiconductor material, a gate that wraps a channel region of the first nanowire and the second nanowire, and source/drain feature that wraps source/drain regions of the first nanowire and the second nanowire. The source/drain feature includes a second semiconductor material that is configured differently than the first semiconductor material. In some implementations, the transistor further includes a fin-like semiconductor layer disposed over a substrate. The first nanowire and the second nanowire are disposed over the fin-like semiconductor layer, such that the first nanowire, the second nanowire, and the fin-like semiconductor layer extend substantially parallel to one another along the same length-wise direction.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Hsiung Lin, Chung-Cheng Wu, Carlos H. Diaz, Chih-Hao Wang, Wen-Hsing Hsieh, Yi-Ming Sheu
  • Patent number: 10665565
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a bump structure disposed on a first substrate and a molding compound in physical contact with the bump structure. The bump structure protrudes from the molding compound. A conductive region is on a second substrate and contacts the bump structure. A no-flow underfill (NUF) material is vertically between the molding compound and the second substrate and laterally surrounds the bump structure. The NUF material is separated from the molding compound.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Jen Lin, Tsung-Ding Wang, Chien-Hsiun Lee, Wen-Hsiung Lu, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20200134250
    Abstract: A semiconductor device includes a first active fin on a substrate; a second active fin on the substrate and separate from the first active fin; and a first fin stub on the substrate, wherein the first fin stub connects a first end of the first active fin and a first end of the second active fin, wherein the fin stub is lower than both the first and the second active fins in height, wherein from a top view the first active fin is oriented lengthwise in a first direction, and the first fin stub is oriented lengthwise in a second direction that is different from the first direction.
    Type: Application
    Filed: December 23, 2019
    Publication date: April 30, 2020
    Inventors: Chung-Ming Wang, Chih-Hsiung Peng, Chi-Kang Chang, Kuei-Shun Chen, Shih-Chi Fu
  • Publication number: 20200126966
    Abstract: An integrated circuit includes a plurality of gate electrode structures extending along a first direction and having a predetermined spatial resolution measurable along a second direction orthogonal to the first direction. The plurality of gate electrode structures includes a first gate electrode structure having a first portion and a second portion separated in the first direction, and a second gate electrode structure having a third portion and a fourth portion separated in the first direction. The integrated circuit further includes a conductive feature including a first section electrically connected to the second portion, wherein the first section extends in the second direction, a second section electrically connected to the third portion, wherein the second section extends in the second direction, and a third section electrically connecting the first section and the second section, the third section extends in a third direction angled with respect to the first and second directions.
    Type: Application
    Filed: December 20, 2019
    Publication date: April 23, 2020
    Inventors: Tung-Heng HSIEH, Hui-Zhong ZHUANG, Chung-Te LIN, Sheng-Hsiung WANG, Ting-Wei CHIANG, Li-Chun TIEN
  • Publication number: 20200126967
    Abstract: An integrated circuit includes a cell layer, a first metal layer, a first conductive via, and a second conductive via. The cell layer includes first and second cells, in which the first cell is separated from the second cell by a non-zero distance. The first metal layer includes a first conductive feature and a second conductive feature, the first conductive feature overlaps the first cell and does not overlap the second cell, and the second conductive feature overlaps the second cell and does not overlap the first cell, in which the first conductive feature is aligned with the second conductive feature along lengthwise directions of the first and second conductive features. The first conductive via interconnects the cell layer and the first conductive feature of the first metal layer. The second conductive via interconnects the cell layer and the second conductive feature of the first metal layer.
    Type: Application
    Filed: December 20, 2019
    Publication date: April 23, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fong-Yuan CHANG, Kuo-Nan YANG, Chung-Hsing WANG, Lee-Chung LU, Sheng-Fong CHEN, Po-Hsiang HUANG, Hiranmay BISWAS, Sheng-Hsiung CHEN, Aftab Alam KHAN
  • Publication number: 20200083341
    Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.
    Type: Application
    Filed: November 13, 2019
    Publication date: March 12, 2020
    Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
  • Publication number: 20200075476
    Abstract: A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over the top surface of the substrate, a pair of first spacers on each sidewall of the first gate structure, a pair of second spacers on each sidewall of the second gate structure, an insulating layer over at least the first gate structure, a first conductive feature over the active region and a second conductive feature over the substrate. Further, the second gate structure is adjacent to the first gate structure and a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature.
    Type: Application
    Filed: November 6, 2019
    Publication date: March 5, 2020
    Inventors: Tung-Heng Hsieh, Ting-Wei Chiang, Chung-Te Lin, Hui-Zhong Zhuang, Li-Chun Tien, Sheng-Hsiung Wang
  • Publication number: 20200038497
    Abstract: The disclosure provides various immunogens comprising a repeat unit of saccharide of Klebsiella pneumoniae CPS, which has a formula selected from the group consisting of Formulae (I) to (VI) as described herein. Also provided are vaccines including one or more immunogens selected from Formula (I) to (VI) and methods of eliciting an immune response against a Klebsiella pneumoniae and preventing infection of Klebsiella pneumoniae by using an immunogen of the invention.
    Type: Application
    Filed: October 3, 2017
    Publication date: February 6, 2020
    Applicants: NATIONAL TAIWAN UNIVERSITY, Academia Sinica
    Inventors: Jin-Town Wang, Shih-Hsiung Wu, Chung-Yi Wu
  • Publication number: 20200030332
    Abstract: The present invention relates to a use of Discoidin Domain Receptor 1 (DDR1) inhibitor in preparing a medicament for preventing or treating a joint disease. The present invention further relates to a use of DDR1 activator in preparing a medicament for preventing or treating abnormalities of endochondral ossification-related conditions.
    Type: Application
    Filed: March 23, 2018
    Publication date: January 30, 2020
    Applicant: Kaohsiung Medical University
    Inventors: Chau-Zen Wang, Chung-Hwan Chen, Liang-Yin Chou, Yu Chou, Mei-Ling Ho, Yi-Hsiung Lin
  • Publication number: 20200006217
    Abstract: A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over the top surface of the substrate, a pair of first spacers on each sidewall of the first gate structure, a pair of second spacers on each sidewall of the second gate structure, an insulating layer over at least the first gate structure, a first conductive feature over the active region and a second conductive feature over the substrate. Further, the second gate structure is adjacent to the first gate structure and a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature.
    Type: Application
    Filed: September 6, 2019
    Publication date: January 2, 2020
    Inventors: Tung-Heng Hsieh, Ting-Wei Chiang, Chung-Te Lin, Hui-Zhong Zhuang, Li-Chun Tien, Sheng-Hsiung Wang
  • Patent number: 10521541
    Abstract: A semiconductor device includes a first active fin on a substrate; a second active fin on the substrate and separate from the first active fin; a first fin stub on the substrate, wherein the first fin stub connects a bottom portion of the first active fin and a bottom portion of the second active fin; and an isolation feature over the first fin stub and between the first and second active fins. The first fin stub is lower than both the first and the second active fins in height. The isolation feature is higher than the first fin stub and lower than both the first and the second active fins in height. From a top view, the first active fin is oriented lengthwise in a first direction, and the first fin stub is oriented lengthwise in a second direction that is different from the first direction.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Ming Wang, Chih-Hsiung Peng, Chi-Kang Chang, Kuei-Shun Chen, Shih-Chi Fu
  • Patent number: 10522527
    Abstract: An integrated circuit includes a plurality of gate electrode structures extending along a first direction and having a predetermined spatial resolution measurable along a second direction orthogonal to the first direction. The plurality of gate electrode structures includes a first gate electrode structure having a first portion and a second portion separated by a first carve-out region, and a conductive feature over the first carve-out region and electrically connecting the first portion and the second portion of the first gate electrode.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tung-Heng Hsieh, Hui-Zhong Zhuang, Chung-Te Lin, Sheng-Hsiung Wang, Ting-Wei Chiang, Li-Chun Tien
  • Patent number: 10515944
    Abstract: An integrated circuit includes a cell layer, a first metal layer, and a first conductive via. The cell layer includes first and second cells, each of which is configured to perform a circuit function. The first metal layer is above the cell layer and includes a first conductive feature that extends from the first cell into the second cell and that is configured to receive a supply voltage. A first conductive via interconnects the cell layer and the metal layer.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fong-Yuan Chang, Kuo-Nan Yang, Chung-Hsing Wang, Lee-Chung Lu, Sheng-Fong Chen, Po-Hsiang Huang, Hiranmay Biswas, Sheng-Hsiung Chen, Aftab Alam Khan
  • Patent number: 10504837
    Abstract: A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over the top surface of the substrate, a pair of first spacers on each sidewall of the first gate structure, a pair of second spacers on each sidewall of the second gate structure, an insulating layer over at least the first gate structure, a first conductive feature over the active region and a second conductive feature over the substrate. Further, the second gate structure is adjacent to the first gate structure and a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Heng Hsieh, Hui-Zhong Zhuang, Chung-Te Lin, Ting-Wei Chiang, Sheng-Hsiung Wang, Li-Chun Tien
  • Patent number: 10497792
    Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: December 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
  • Publication number: 20190272965
    Abstract: A load control system includes a power switching device and a control device, wherein the power switching device includes a first power input port, a second power input port and a power output port. The first power input port and the second power input port are electrically connected to a first battery and a second battery respectively, and the power output port is electrically connected to the control device. The power output port receives the power which is input to the first power input port or the second power input port so as to supply the power to the control device. The control device is adapted to control a load to switch and to control the power switching device to utilize the power from the first power input port and the second power input port alternatively, thereby extending the respective usage time of the first battery and the second battery.
    Type: Application
    Filed: March 2, 2018
    Publication date: September 5, 2019
    Applicant: GRAND MATE CO., LTD.
    Inventors: CHUNG-CHIN HUANG, CHIN-YING HUANG, HSIN-MING HUANG, HSING-HSIUNG HUANG, YEN-JEN YEH, CHIA-YU WANG
  • Publication number: 20190148352
    Abstract: An integrated circuit includes a cell layer, a first metal layer, and a first conductive via. The cell layer includes first and second cells, each of which is configured to perform a circuit function. The first metal layer is above the cell layer and includes a first conductive feature that extends from the first cell into the second cell and that is configured to receive a supply voltage. A first conductive via interconnects the cell layer and the metal layer.
    Type: Application
    Filed: September 5, 2018
    Publication date: May 16, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fong-Yuan CHANG, Kuo-Nan YANG, Chung-Hsing WANG, Lee-Chung LU, Sheng-Fong CHEN, Po-Hsiang HUANG, Hiranmay BISWAS, Sheng-Hsiung CHEN, Aftab Alam KHAN