Abstract: A method performed by at least one processor includes the following steps: generating a layout of an integrated circuit (IC), the layout including a cell and a layout context in a vicinity of the cell; determining a representative context group for the cell from a set of predetermined context groups; determining a representative timing table corresponding to the representative context group, the representative timing table including a best-case delay value and a worst-case delay value; and performing a timing analysis on the layout according to the best-case delay value and the worst-case delay value.

Abstract: A system including memory devices and a tester is provided. The tester is configured to: generate a first multi-purpose command to the memory devices and a first data signal to each of a first group in the memory devices to store a first identity; generate a second multi-purpose command to the memory devices and the first data signal to each of a second group in the memory devices to store a second identity; generate a third multi-purpose command and a fourth multi-purpose command to the memory devices to select the first and second groups in the memory devices to have first and second time shifts in write leveling pulses therein separately; transmit a write datum to the memory devices for performing a write operation to the memory devices; and receive read data and compare the write datum and the read data for a test result.

Abstract: A glass composition includes, based on 100 wt % of the glass composition, silicon dioxide present in an amount ranging from 45 wt % to 61 wt %, aluminum oxide present in an amount (A) ranging from 15 wt % to 22 wt %, calcium oxide present in an amount (C) ranging from 0.1 wt % to 6 wt %, magnesium oxide present in an amount (M) of greater than 0 wt % and lower than 2 wt %, zinc oxide present in an amount of greater than 0 wt % and lower than 8 wt %, copper oxide present in an amount of greater than 0 wt % and lower than 7 wt %, and boron oxide present in an amount of greater than 6 wt % and lower than 18 wt %. A glass fiber including the glass composition, and an electronic product including the glass fiber are also provided.

Abstract: Systems and methods for context aware circuit design are described herein. A method includes: identifying at least one cell to be designed into a circuit; identifying at least one context parameter having an impact to layout dependent effect of the circuit; generating, for each cell and for each context parameter, a plurality of abutment environments associated with the cell; estimating, for each cell and each context parameter, a sensitivity of at least one electrical property of the cell to the context parameter by generating a plurality of electrical property values of the cell under the plurality of abutment environments; and determining whether each context parameter is a key context parameter for a static analysis of the circuit, based on the sensitivity of the at least one electrical property of each cell and based on at least one predetermined threshold.

Abstract: The present disclosure provides a molding system for fabricating a FRP composite article. The molding system includes a detector, a resin dispenser, a processing module, and a molding machine. The detector is configured to capture a graph of a woven fiber from a top view. The resin dispenser is configured to provide a resin to the woven fiber to form a FRP. The processing module is configured to receive the graph and a plurality of parameters of the FRP. The processing module includes a CNN model, and is configured to use the CNN model to obtain a plurality of predicted mechanical properties of the FRP according to the graph and the plurality of parameters of the FRP. The molding machine is configured to mold the FRP to fabricate the FRP composite article according to the plurality of predicted mechanical properties.

Abstract: A vacuum forming method for a membrane-like object having a protruding structure and its forming apparatus, the forming method includes the following steps: fixing a flat membrane having a protruding structure on a sealing device; fixing a product model on a vacuum pumping device; clamping a transfer device on the protruding structure; utilizing a heating device to heat the flat membrane for softening the flat membrane; controlling the transfer device to move the protruding structure to a predetermined forming position; fitting the sealing device tightly to the vacuum pumping device; pumping out air between the flat membrane and the product model by the vacuum pumping device to generate negative pressure, so that the flat membrane is completely attached to a surface of the product model to form a final membrane having the protruding structure; after cooling, the final membrane having the protruding structure is taken out of the cooling room.

Abstract: Routing substrates, methods of manufacture, and electronic assemblies including routing substrates are described. In an embodiment, a routing substrate includes a plurality of metal routing layers, a plurality of dielectric layers including a top dielectric layer forming a topmost surface, and a cavity formed in the topmost surface. The cavity may include a bottom cavity surface, a first plurality of first surface mount (SMT) metal bumps embedded within the top dielectric layer and protruding from the topmost surface of the top dielectric layer, and a second plurality of second SMT metal bumps embedded within an intermediate dielectric layer of the plurality of dielectric layers and protruding from the bottom cavity surface.

Abstract: A method performed by at least one processor includes the following steps: generating a layout of an integrated circuit (IC), the layout comprising a cell and a layout context in a vicinity of the cell; receiving from a library a set of context groups and a set of timing tables, wherein each of the context groups is associated with one of the set of timing tables; determining a representative context group for the cell through comparing the layout context of the cell with the set of context groups; and performing a timing analysis on the layout according to a representative timing table associated with the representative context group for the cell.

Abstract: A nebulizer includes a medication adjustment member and a nebulizing module. The medication adjustment device includes a liquid reservoir and a medication adjustment member. The liquid reservoir includes a first opening and a second opening. The liquid reservoir includes an accommodating cavity, and the first opening communicates with the second opening through the accommodating cavity. The medication adjustment member is detachably disposed on the first opening and located in the accommodating cavity. The medication adjustment member includes a third opening and an adjustment opening. The medication adjustment member includes an adjustment chamber therein. The third opening communicates with the adjustment opening, and the adjustment opening communicates with the second opening. The nebulizing module is disposed inside the liquid reservoir. The nebulizing module is located at a connection position between the second opening and the accommodating cavity.

Abstract: Systems and methods for context aware circuit design are described herein. A method includes: identifying at least one cell to be designed into a circuit; identifying at least one context parameter having an impact to layout dependent effect of the circuit; generating, for each cell and for each context parameter, a plurality of abutment environments associated with the cell; estimating, for each cell and each context parameter, a sensitivity of at least one electrical property of the cell to the context parameter by generating a plurality of electrical property values of the cell under the plurality of abutment environments; and determining whether each context parameter is a key context parameter for a static analysis of the circuit, based on the sensitivity of the at least one electrical property of each cell and based on at least one predetermined threshold.

Abstract: A system is provided. The system comprises a memory device and a test device. The test device that is operatively coupled to the memory device and transmits a plurality of glitch signals and a plurality of control signals after the plurality of glitch signals for a write operation of the memory device according to a data signal. The test device determines, based on write data of the data signal, whether read data outputted in a read operation of the memory device are bitwise shifted to generate a test result indicating a disturbance to the write operation induced by the plurality of glitch signals.

Abstract: A semiconductor memory device includes a substrate, a memory cell contact formed over the substrate, a bit line conductive structure formed over the substrate and a dielectric spacer located between the memory cell contact and the bit line conductive structure. The dielectric spacer includes an air gap having a rectangular cross-section, and the rectangular cross-section has a height H and a width W, wherein a H/W ratio is equal to or greater than 40.

Abstract: The present disclosure provides a memory device and the forming method thereof. The memory device includes a bit line on a substrate, a multilayer spacer covering the bit line, a low-k dielectric layer and an air gap interposed in the multilayer spacer, and a cell contact adjacent to the multilayer spacer. The multilayer spacer, the low-k dielectric layer, and the air gap are disposed between the bit line and the cell contact. The top surface of the low-k dielectric layer is lower than a top surface of the bit line. The air gap is above the low-k dielectric layer, and an orthogonal projection of the air gap onto the substrate is partially overlapped with that of the low-k dielectric layer onto the substrate.

Abstract: An integrated circuit is provided and includes first transistors of a first circuit arranged in a first cell row having a first number of fin structures and a second transistor of a second circuit. The second transistor is coupled in parallel with a first element in the first transistors between first and second terminals of the first circuit, and arranged in a second cell row having a second number, different from the first number, of fin structures. The first element and the second transistor share a first gate extending in a first direction to pass through the first and second cell rows in a layout view. The second transistor is a duplication of the first element.

Abstract: A semiconductor structure includes a circuit with a redistribution layer (RDL) formed over the circuit. The redistribution layer comprises a plurality of metal layers. An inductor is formed in a topmost metal layer, and the circuit is located directly under the inductor. An under bump metallization (UBM) layer formed on the topmost metal layer and a conductive connector formed on the UBM layer.

Abstract: A method for detecting a three-dimensional object in a two-dimensional image includes: inputting the two-dimensional image into an object detection model, and obtaining a resulting detection depth dataset; obtaining, based on the detection depth dataset, coordinate sets of a number of points-of-interest each associated with a to-be-detected object in a 3D camera centered coordinate system; and converting the coordinate sets of the number of points-of-interest in the 3D camera centered coordinate system into a number of coordinate sets in a 3D global coordinate system. Embodiments of this disclosure may be utilized in the field of self-driving cars with roadside traffic cameras.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate having an active region and a shallow trench isolation (STI) adjacent to the active region of the substrate. The STI includes a charge trapping layer and a liner disposed between the charge trapping layer and the active region of the substrate, wherein the charge trapping layer is doped with an impurity.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate and a first isolation structure. The substrate has a cell region and a peripheral region. The first isolation structure is disposed in the cell region of the substrate. The first isolation structure includes a first dielectric layer and a second dielectric layer. The second dielectric layer is spaced apart from the substrate by the first dielectric layer. The second dielectric layer is doped with an impurity.

Abstract: A semiconductor device includes several first cell row an several second cell rows. The first cell rows extend in a first direction. Each of the first cell rows has a first row height. A first row of the first cell rows is configured for a first cell to be arranged. The second cell rows extend in the first direction. Each of the second cell rows has a second row height that is different from the first row height. At least one row of the second cell rows includes a portion for at least one second cell to be arranged. The portion has a third row height that is different from the first row height and the second row height.