Patents by Inventor Chung Hsu

Chung Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240241414
    Abstract: A reflective display panel includes a first substrate and a second substrate. A thin film transistor and a reflective layer are disposed on the first substrate. A color resist layer is disposed on the second substrate. The reflective display panel includes a color sub-pixel region and a white sub-pixel region adjacent to each other. The color sub-pixel region has the color resist layer, and the white sub-pixel region has no color resist layer. A buffer layer is disposed in the white sub-pixel region on the first substrate or the second substrate. A cell gap between the first substrate and the second substrate in the white sub-pixel region is smaller than a cell gap between the first substrate and the second substrate in the color sub-pixel region. In this way, reflectivity and chromaticity can be improved.
    Type: Application
    Filed: December 4, 2023
    Publication date: July 18, 2024
    Inventors: Wei-Chih HSU, Ding-Wei LIU, Yen-Chung CHEN, Cheng-Yen YEH, Chen-Hao SU
  • Patent number: 12040219
    Abstract: A device includes a substrate, a first fin, a second fin, a first isolation structure, a second isolation structure, and a gate structure. The first fin extends from a p-type region of the substrate. The second fin extends from an n-type region of the substrate. The first isolation structure is over the p-type region and adjacent to the first fin. The first isolation structure has a bottom surface and opposite first and second sidewalls connected to the bottom surface, a first round corner is between the bottom surface and the first sidewall of the first isolation structure, and the first sidewall is substantially parallel to the second sidewall. The second isolation structure is over the n-type region and adjacent to the first fin. The first isolation structure is deeper than the second isolation structure. The gate structure is over the first isolation structure and covering the first fin.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: July 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Chung Huang, Chiung-Wen Hsu, Mei-Ju Kuo, Yu-Ting Weng, Yu-Chi Lin, Ting-Chung Wang, Chao-Cheng Chen
  • Publication number: 20240166486
    Abstract: An automated beverage preparation apparatus includes: multiple pumps for extracting multiple fluid materials stored in multiple material containers, and pushing the extracted fluid materials to move forward; a fluid output device coupled with the multiple pumps and arranged to operably dispense fluid materials to a beverage container; a user control interface arranged to operably generate a control command; a processing circuit arranged to operably generate a corresponding control signal according to the control command; and a pump control circuit arranged to operably control the multiple pumps according to the control signal. The pump control circuit conducts a sparkling drink making operation under control of the processing circuit to cause the fluid output device to dispense different fluid materials to the beverage container in order, so as to automatically form a sparkling drink/aerated drink with a predetermined flavor within the beverage container.
    Type: Application
    Filed: January 19, 2023
    Publication date: May 23, 2024
    Applicant: Botrista Technology, Inc.
    Inventors: Yung-Hsiang CHANG, Wu-Chou KUO, Kuan-Chang PAN, Kai-Chung HSU, Jhih-Sheng JHANG
  • Publication number: 20240164569
    Abstract: An automated beverage preparation apparatus includes: multiple pumps for extracting multiple fluid materials stored in multiple material containers, and pushing the extracted fluid materials to move forward; a fluid output device coupled with the multiple pumps and arranged to operably dispense fluid materials to a beverage container; a user control interface arranged to operably generate a control command; a processing circuit arranged to operably generate a corresponding control signal according to the control command; and a pump control circuit arranged to operably control the multiple pumps according to the control signal. The pump control circuit conducts a layered drink making operation under control of the processing circuit to cause the fluid output device to dispense different fluid materials to the beverage container, so as to automatically form a layered drink/gradient drink having at least two color layers within the beverage container.
    Type: Application
    Filed: January 19, 2023
    Publication date: May 23, 2024
    Applicant: Botrista Technology, Inc.
    Inventors: Yung-Hsiang CHANG, Wu-Chou KUO, Kuan-Chang PAN, Kai-Chung HSU, Jhih-Sheng JHANG
  • Patent number: 11988867
    Abstract: The present disclosure provides a package structure having a photonic integrated circuit, the package structure includes a substrate, a chip and an optical module. The chip has an optical waveguide structure and a recessed portion. The optical waveguide structure is adjacent to the recessed portion. The recessed portion faces the substrate, and the chip is engaged to the substrate by flip chip. The optical module is provided in the recessed portion of the chip.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: May 21, 2024
    Assignee: Molex, LLC
    Inventors: Chih-Wei Peng, Chih-Chung Hsu, Chih-Chung Wu, Zuon-Min Chuang
  • Patent number: 11988934
    Abstract: An electronic device includes: a first light modulation assembly, including: a first substrate; a second substrate opposite to the first substrate; a first conductive layer disposed on the first substrate; a second conductive layer disposed on the second substrate; a first insulating layer disposed on the first substrate; and a first light modulation layer disposed between the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: May 21, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Bi-Ly Lin, Rong-Jyun Lin, I-Wen Yang, Chih-Chung Hsu
  • Publication number: 20240162182
    Abstract: An asymmetric stackup structure for an SoC package substrate is disclosed. The package substrate may include a substrate with one or more insulating material layers. A first recess may be formed in an upper surface of the substrate. The recess may be formed down to a conductive layer in the substrate. An integrated passive device may be positioned in the recess. A plurality of build-up layers may be formed on top of the substrate. At least one via path may be formed through the build-up layers and the substrate to connect contacts on the lower surface of the substrate to contacts on the upper surface of the build-up layers.
    Type: Application
    Filed: November 17, 2023
    Publication date: May 16, 2024
    Inventors: Yikang Deng, Taegui Kim, Yifan Kao, Jun Chung Hsu
  • Patent number: 11982369
    Abstract: An air valve structure arranged on a base comprises an air plug and a state-switching component. The air plug is arranged in an air chamber in an axial direction. The air plug includes a closing state to close the air hole, and an opening state to open the air hole. The state-switching component comprises a driving member that links the air plug, a shape-memory alloy (SMA) wire connected with the driving member, and at least one conductive member connected with the SMA wire. The driving member exerts an acting force to the air plug based on a condition of electricity provided by the conductive member for the SMA wire. The direction of the acting force is non-parallel with the axial direction and the air plug is moved and changed between the closing state and the opening state by the acting force.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: May 14, 2024
    Assignee: TANGTRING SEATING TECHNOLOGY INC
    Inventors: Tsun-Hsiang Wen, Shih-Chung Hsu, Jun Xie, Jian Zeng, Xian-Chang Zou
  • Patent number: 11976170
    Abstract: The present invention provides a polybenzoxazole precursor, which comprises a structure of formula (I): wherein the definitions of Y, Z, R1, i, j, and V are provided herein. By means of the polybenzoxazole precursor, the resin composition of the present invention is able to form a film with high frequency characteristics and high contrast.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: May 7, 2024
    Assignee: MICROCOSM TECHNOLOGY CO., LTD.
    Inventors: Steve Lien-chung Hsu, Yu-Ching Lin, Yu-Chiao Shih, Hou-Chieh Cheng
  • Publication number: 20240095434
    Abstract: A method performed by at least one processor includes the following steps: generating a layout of an integrated circuit (IC), the layout comprising a cell and a layout context in a vicinity of the cell; receiving from a library a set of context groups and a set of timing tables, wherein each of the context groups is associated with one of the set of timing tables; determining a representative context group for the cell through comparing the layout context of the cell with the set of context groups; and performing a timing analysis on the layout according to a representative timing table associated with the representative context group for the cell.
    Type: Application
    Filed: November 23, 2023
    Publication date: March 21, 2024
    Inventors: ZHE-WEI JIANG, JERRY CHANG JUI KAO, SUNG-YEN YEH, LI CHUNG HSU
  • Patent number: 11908819
    Abstract: Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.
    Type: Grant
    Filed: October 12, 2022
    Date of Patent: February 20, 2024
    Assignee: Apple Inc.
    Inventors: Jun Chung Hsu, Chih-Ming Chung, Jun Zhai, Yifan Kao, Young Doo Jeon, Taegui Kim
  • Publication number: 20240030069
    Abstract: An integrated circuit includes a first cell and a second cell. The first cell has a first height along a first direction. The second cell has a second height shorter than the first height along the first direction. A transistor of the first cell and a transistor of the second cell share a first active area, and a first boundary of the first cell, a first boundary of the second cell, a second boundary of the first cell and a second boundary of the second cell are arranged in order along the first direction.
    Type: Application
    Filed: September 22, 2023
    Publication date: January 25, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jerry Chang-Jui KAO, Hui-Zhong ZHUANG, Li-Chung HSU, Sung-Yen YEH, Yung-Chen CHIEN, Jung-Chan YANG, Tzu-Ying LIN
  • Publication number: 20240004033
    Abstract: A light sensor and a control method thereof are revealed. The light sensor comprises a first light-emitting element, a second light-emitting element and a light-sensing element. The first light-emitting element is used to generate a first emitting signal. The first emitting signal has an optical wavelength within a first wavelength range. The second light-emitting element is used to generate a second emitting signal. The wavelength of the second emitting signal has an optical wavelength within a second wavelength range. The first wavelength range is different from the second wavelength range. Thereby, a control circuit sequentially controls the first light-emitting element and the second light emitting-element to emit the first emitting signal and the second emitting signal.
    Type: Application
    Filed: January 24, 2023
    Publication date: January 4, 2024
    Inventors: Han-Chung Hsu, Feng-Jung Hsu
  • Patent number: 11857834
    Abstract: A workout device includes a base frame, a top cover and a gliding mechanism. The base frame includes a chassis and through holes formed in the chassis. The top cover includes dome structures aligned with the through holes, respectively, when the top cover is assembled to the base frame. The gliding mechanism consists of multi-directional rotating members accommodated in the dome structures and partially protruding from the through holes, respectively, when the top cover is assembled to the base frame. In response to a pressing force exerted onto the cover body, the dome structures are in contact with the multi-directional rotating members so as to cause friction therebetween, and the friction changes with the force exerted onto the cover body.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: January 2, 2024
    Assignee: CHIN CHARNG INDUSTRIAL CO., LTD
    Inventor: Wen-Chung Hsu
  • Patent number: 11862597
    Abstract: An asymmetric stackup structure for an SoC package substrate is disclosed. The package substrate may include a substrate with one or more insulating material layers. A first recess may be formed in an upper surface of the substrate. The recess may be formed down to a conductive layer in the substrate. An integrated passive device may be positioned in the recess. A plurality of build-up layers may be formed on top of the substrate. At least one via path may be formed through the build-up layers and the substrate to connect contacts on the lower surface of the substrate to contacts on the upper surface of the build-up layers.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: January 2, 2024
    Assignee: Apple Inc.
    Inventors: Yikang Deng, Taegui Kim, Yifan Kao, Jun Chung Hsu
  • Patent number: 11853676
    Abstract: A method performed by at least one processor includes the following steps: generating a layout of an integrated circuit (IC), the layout comprising a cell and a layout context in a vicinity of the cell; receiving from a library a set of context groups and a set of timing tables, wherein each of the context groups is associated with one of the set of timing tables; determining a representative context group for the cell through comparing the layout context of the cell with the set of context groups; and performing a timing analysis on the layout according to a representative timing table associated with the representative context group for the cell.
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Zhe-Wei Jiang, Jerry Chang Jui Kao, Sung-Yen Yeh, Li Chung Hsu
  • Publication number: 20230402390
    Abstract: Improved redistribution layer structures for integrated circuit or system-on-chip (SoC) packages substrate are disclosed. Via landing pads and via interconnects in the redistribution layers are self-aligning with the centers of the vias aligning with the pads. This self-alignment may allow pads that terminate non-stacked vias to have decreased widths or diameters without extra capture space. The redistribution layers have vias with vertical or near vertical sidewalls. Vias may also have various shapes, widths, or lengths. Traces in the redistribution layers may have various lengths and shapes with lengths that may extend into layers routing the vias to provide increased metal density in the traces.
    Type: Application
    Filed: June 13, 2022
    Publication date: December 14, 2023
    Inventors: Ryan Mesch, Jun Chung Hsu
  • Publication number: 20230401369
    Abstract: Systems and methods for context aware circuit design are described herein. A method includes: identifying at least one cell to be designed into a circuit; identifying at least one context parameter having an impact to layout dependent effect of the circuit; generating, for each cell and for each context parameter, a plurality of abutment environments associated with the cell; estimating, for each cell and each context parameter, a sensitivity of at least one electrical property of the cell to the context parameter by generating a plurality of electrical property values of the cell under the plurality of abutment environments; and determining whether each context parameter is a key context parameter for a static analysis of the circuit, based on the sensitivity of the at least one electrical property of each cell and based on at least one predetermined threshold.
    Type: Application
    Filed: August 10, 2023
    Publication date: December 14, 2023
    Inventors: Li-Chung HSU, Yen-Pin CHEN, Sung-Yen YEH, Jerry Chang-Jui KAO, Chung-Hsing WANG
  • Publication number: 20230392707
    Abstract: An air valve structure arranged on a base comprises an air plug and a state-switching component. The air plug is arranged in an air chamber in an axial direction. The air plug includes a closing state to close the air hole, and an opening state to open the air hole. The state-switching component comprises a driving member that links the air plug, a shape-memory alloy (SMA) wire connected with the driving member, and at least one conductive member connected with the SMA wire. The driving member exerts an acting force to the air plug based on a condition of electricity provided by the conductive member for the SMA wire. The direction of the acting force is non-parallel with the axial direction and the air plug is moved and changed between the closing state and the opening state by the acting force.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 7, 2023
    Inventors: Tsun-Hsiang WEN, Shih-Chung HSU, Jun XIE, Jian ZENG, Xian-Chang ZOU
  • Publication number: 20230377976
    Abstract: An integrated circuit is provided and includes first transistors of a first circuit arranged in a first cell row having a first number of fin structures and a second transistor of a second circuit. The second transistor is coupled in parallel with a first element in the first transistors between first and second terminals of the first circuit, and arranged in a second cell row having a second number, different from the first number, of fin structures. The first element and the second transistor share a first gate extending in a first direction to pass through the first and second cell rows in a layout view. The second transistor is a duplication of the first element.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 23, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jerry Chang-Jui KAO, Hui-Zhong ZHUANG, Li-Chung HSU, Sung-Yen YEH, Yung-Chen CHIEN, Jung-Chan YANG, Tzu-Ying LIN