Patents by Inventor Chung-Hsuan Wang
Chung-Hsuan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096718Abstract: A testkey structure includes a substrate, a control gate, a metal gate, a dielectric structure, a source line, and a drain line. The control gate is disposed over the substrate and includes a first region and a second region. The second region is adjacent to the first region. The first region has a first conductivity type, and the second region has a second conductivity type. The second conductivity type is different from the first conductivity type. The metal gate is disposed over the control gate. The dielectric structure is embedded in the metal gate and divides the metal gate into a first part and a second part. The dielectric structure is adjacent to the junction between the first region and the second region. The dielectric structure is in contact with the control gate. The source line and the drain line are disposed on opposite sides of the control gate.Type: ApplicationFiled: September 15, 2022Publication date: March 21, 2024Inventor: Chung-Hsuan WANG
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Patent number: 11920055Abstract: A process for producing a barrier composition includes subjecting a siloxane compound having 1 to 3 amino groups and an aqueous solution including water and an alcohol to hydrolysis and first-stage condensation under required conditions, subjecting a first colloidal mixture obtained and an additional alcohol to second-stage condensation, subjecting a second colloidal mixture obtained, which has a particular solid content, to heating under required conditions, and subjecting a cured product obtained to aging under required conditions. A barrier composition produced by the process is also disclosed.Type: GrantFiled: October 26, 2021Date of Patent: March 5, 2024Assignee: NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGYInventors: Chung-Kuang Yang, Yi-Hsuan Lai, Sheng-Tung Huang, Kun-Li Wang
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Publication number: 20230209823Abstract: Provided is a method of manufacturing a memory device and a patterning method. The patterning method includes following steps. A control structure including stop layers and oxide layers stacked alternately, a hard mask layer, and a mask pattern are sequentially formed on a target layer. A photoresist layer is formed in the mask pattern on the hard mask layer. A portion of the hard mask layer and a portion of the control structure are removed to form first openings by using the photoresist layer and the mask pattern as a mask. The photoresist layer and the hard mask layer are removed to form a second opening having a bottom surface higher than that of the first openings. At least one etching process is performed so that the first and second openings extend into and divide the control structure and the target layer into stack structures.Type: ApplicationFiled: March 5, 2023Publication date: June 29, 2023Applicant: Winbond Electronics Corp.Inventor: Chung-Hsuan Wang
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Patent number: 11631685Abstract: Provided is a memory device including a substrate, a plurality of first stack structures, and a plurality of second stack structures. The substrate includes an array region and a periphery region. The first stack structures are disposed on the substrate in the array region. Each first stack structure sequentially includes: a first tunneling dielectric layer, a first floating gate, a first inter-gate dielectric layer, a first control gate, a first metal layer, a first cap layer, and the first stop layer. The second stack structures are disposed on the substrate in the periphery region. Each second stack structure sequentially includes: a second tunneling dielectric layer, a second floating gate, a second inter-gate dielectric layer, a second control gate, a second metal layer, a second cap layer, and the second stop layer. The first stack structures have a pattern density greater than a pattern density of the second stack structures.Type: GrantFiled: August 26, 2021Date of Patent: April 18, 2023Assignee: Winbond Electronics Corp.Inventor: Chung-Hsuan Wang
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Publication number: 20220320126Abstract: Provided is a memory device including a substrate, a plurality of first stack structures, and a plurality of second stack structures. The substrate includes an array region and a periphery region. The first stack structures are disposed on the substrate in the array region. Each first stack structure sequentially includes: a first tunneling dielectric layer, a first floating gate, a first inter-gate dielectric layer, a first control gate, a first metal layer, a first cap layer, and the first stop layer. The second stack structures are disposed on the substrate in the periphery region. Each second stack structure sequentially includes: a second tunneling dielectric layer, a second floating gate, a second inter-gate dielectric layer, a second control gate, a second metal layer, a second cap layer, and the second stop layer. The first stack structures have a pattern density greater than a pattern density of the second stack structures.Type: ApplicationFiled: August 26, 2021Publication date: October 6, 2022Applicant: Winbond Electronics Corp.Inventor: Chung-Hsuan Wang
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Patent number: 11418221Abstract: The disclosure provides a method and a polar code decoder for determining a to-be-flipped bit position when performing a successive cancellation list flip operation. The method includes: obtaining a polar code decoding tree generated by performing a successive cancellation list (SCL) operation on a polar code segment, and the polar code segment includes multiple bit positions, and each bit position in the polar code decoding tree includes multiple surviving paths and multiple pruned paths; in a post-processing stage for the SCL operation, estimating a correct path probability of each of the surviving paths and the pruned paths of the i-th bit position and accordingly estimating a reliability for the i-th bit position; selecting a specific bit position among the bit positions based on the reliability of each bit position; and performing an SCL flip operation on the polar code decoding tree based on the specific bit position.Type: GrantFiled: January 25, 2021Date of Patent: August 16, 2022Assignee: National Tsing Hua UniversityInventors: Chung-Hsuan Wang, Yi-Han Pan, Yu-Heng Lin, Yeong-Luh Ueng, Chin-Liang Wang
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Publication number: 20220149868Abstract: The disclosure provides a method and a polar code decoder for determining a to-be-flipped bit position when performing a successive cancellation list flip operation. The method includes: obtaining a polar code decoding tree generated by performing a successive cancellation list (SCL) operation on a polar code segment, and the polar code segment includes multiple bit positions, and each bit position in the polar code decoding tree includes multiple surviving paths and multiple pruned paths; in a post-processing stage for the SCL operation, estimating a correct path probability of each of the surviving paths and the pruned paths of the i-th bit position and accordingly estimating a reliability for the i-th bit position; selecting a specific bit position among the bit positions based on the reliability of each bit position; and performing an SCL flip operation on the polar code decoding tree based on the specific bit position.Type: ApplicationFiled: January 25, 2021Publication date: May 12, 2022Applicant: National Tsing Hua UniversityInventors: Chung-Hsuan Wang, Yi-Han Pan, Yu-Heng Lin, Yeong-Luh Ueng, Chin-Liang Wang
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Patent number: 11316106Abstract: Provided are a resistive random access memory and a manufacturing method thereof. The resistive random access memory includes first, second, and third electrodes, a variable resistance layer, a selection layer, and first and second bit lines. The second electrode and the third electrode are on the first electrode. The second and third electrodes are separated from each other and overlapped with the sidewall and the top surface of the first electrode. The variable resistance layer is between the first and second electrodes and between the first and third electrodes. The selection layer is between the variable resistance layer and the first electrode. The first bit line is on the second electrode and electrically connected to the second electrode via a first contact. The second bit line is on the third electrode and electrically connected to the third electrode via a second contact.Type: GrantFiled: December 2, 2020Date of Patent: April 26, 2022Assignee: Winbond Electronics Corp.Inventors: Chung-Hsuan Wang, Yu-Ting Chen, Tz-Hau Guo, Chang-Hsuan Wu, Chiung-Lin Hsu
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Publication number: 20210193918Abstract: Provided are a resistive random access memory and a manufacturing method thereof. The resistive random access memory includes first, second, and third electrodes, a variable resistance layer, a selection layer, and first and second bit lines. The second electrode and the third electrode are on the first electrode. The second and third electrodes are separated from each other and overlapped with the sidewall and the top surface of the first electrode. The variable resistance layer is between the first and second electrodes and between the first and third electrodes. The selection layer is between the variable resistance layer and the first electrode. The first bit line is on the second electrode and electrically connected to the second electrode via a first contact. The second bit line is on the third electrode and electrically connected to the third electrode via a second contact.Type: ApplicationFiled: December 2, 2020Publication date: June 24, 2021Applicant: Winbond Electronics Corp.Inventors: Chung-Hsuan Wang, Yu-Ting Chen, Tz-Hau Guo, Chang-Hsuan Wu, Chiung-Lin Hsu
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Patent number: 10770555Abstract: The present disclosure relates to a semiconductor device. The semiconductor device includes a gate structure disposed on a semiconductor substrate, a sidewall spacer disposed on sidewalls of the gate structure, a lightly-doped source/drain region formed in the semiconductor substrate on opposite sides of the gate structure, a source/drain region formed in the semiconductor substrate on opposite sides of the sidewall spacer, a halo implant region formed in the semiconductor substrate below the gate structure and adjacent to the lightly-doped source/drain region, and a counter-doping region formed in the semiconductor substrate below the gate structure and between the lightly-doped source/drain region and the halo implant region. The dopant concentration of the counter-doping region is lower than the dopant concentration of the halo implant region.Type: GrantFiled: July 25, 2017Date of Patent: September 8, 2020Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Chung-Hsuan Wang, Kan-Sen Chen, Sing-Lin Wu, Yung-Lung Chou, Yun-Chou Wei, Chia-Hao Lee, Chih-Cherng Liao
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Publication number: 20190035900Abstract: The present disclosure relates to a semiconductor device. The semiconductor device includes a gate structure disposed on a semiconductor substrate, a sidewall spacer disposed on sidewalls of the gate structure, a lightly-doped source/drain region formed in the semiconductor substrate on opposite sides of the gate structure, a source/drain region formed in the semiconductor substrate on opposite sides of the sidewall spacer, a halo implant region formed in the semiconductor substrate below the gate structure and adjacent to the lightly-doped source/drain region, and a counter-doping region formed in the semiconductor substrate below the gate structure and between the lightly-doped source/drain region and the halo implant region. The dopant concentration of the counter-doping region is lower than the dopant concentration of the halo implant region.Type: ApplicationFiled: July 25, 2017Publication date: January 31, 2019Applicant: Vanguard International Semiconductor CorporationInventors: Chung-Hsuan WANG, Kan-Sen CHEN, Sing-Lin WU, Yung-Lung CHOU, Yun-Chou WEI, Chia-Hao LEE, Chih-Cherng LIAO
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Patent number: 9978864Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a first conductive type well region; a gate structure; a lightly-doped drain region and a lightly-doped source region disposed at two opposite sides of the gate structure; a second conductive type first doped region disposed in the lightly-doped drain region, wherein the doping concentration of the second conductive type first doped region is less than the doping concentration of the lightly-doped drain region; a heavily-doped source region disposed in the lightly-doped source region; and a heavily-doped drain region disposed in the second conductive type first doped region. The present disclosure also provides a method for manufacturing the semiconductor device.Type: GrantFiled: December 3, 2015Date of Patent: May 22, 2018Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Tse-Hsiao Liu, Sing-Lin Wu, Chung-Hsuan Wang, Yung-Lung Chou, Chia-Hao Lee, Chih-Cherng Liao
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Publication number: 20170162691Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a first conductive type well region; a gate structure; a lightly-doped drain region and a lightly-doped source region disposed at two opposite sides of the gate structure; a second conductive type first doped region disposed in the lightly-doped drain region, wherein the doping concentration of the second conductive type first doped region is less than the doping concentration of the lightly-doped drain region; a heavily-doped source region disposed in the lightly-doped source region; and a heavily-doped drain region disposed in the second conductive type first doped region. The present disclosure also provides a method for manufacturing the semiconductor device.Type: ApplicationFiled: December 3, 2015Publication date: June 8, 2017Applicant: Vanguard International Semiconductor CorporationInventors: Tse-Hsiao LIU, Sing-Lin WU, Chung-Hsuan WANG, Yung-Lung CHOU, Chia-Hao LEE, Chih-Cherng LIAO
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Patent number: 8468410Abstract: An address generation apparatus for quadratic permutation polynomial (QPP) interleaver receives several configurable parameters and uses a plurality of QPP units to compute and outputs a plurality of interleaving addresses according to a QPP function ?(i)=(f1i+f2i2) mod k, where f1 and f2 are QPP coefficients, k is information block length of an input sequence, 0?i?k?1, and mod is a modulus operation. Each of the plurality of QPP units is a parallel computation unit, and outputs in parallel a corresponding group of interleaver addresses, where ?(i) is also a ith interleaving address generated by the apparatus.Type: GrantFiled: September 28, 2010Date of Patent: June 18, 2013Assignees: Industrial Technology Research Institute, National Chiao Tung UniversityInventors: Shuenn-Gi Lee, Chung Hsuan Wang, Wern-Ho Sheen
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Patent number: 8332701Abstract: An address generation apparatus for a quadratic permutation polynomial (QPP) interleaver is provided. It comprises a basic recursive unit, and L recursive units represented by first recursive unit up to Lth recursive units. The apparatus inputs a plurality of configurable parameters according to a QPP function ?(i)=(f1i+f2i2) mod k, generates a plurality of interleaver addresses in serial via the basic recursive unit, and generates L groups of corresponding interleaver addresses via the first up to the Lth recursive units, wherein ?(i) is the i-th interleaver address generated by the apparatus, f1 and f2 are QPP coefficients, and k is information block length of an input sequence, 0?i?k?1.Type: GrantFiled: December 25, 2009Date of Patent: December 11, 2012Assignees: Industrial Technology Research Institute, National Chiao Tung UniversityInventors: Shuenn-Gi Lee, Chung-Hsuan Wang, Wern-Ho Sheen
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Publication number: 20120047414Abstract: An address generation apparatus for quadratic permutation polynomial (QPP) interleaver receives several configurable parameters and uses a plurality of QPP units to compute and outputs a plurality of interleaving addresses according to a QPP function ?(i)=(f1i+f2i2) mod k, where f1 and f2 are QPP coefficients, k is information block length of an input sequence, 0?i?k?1, and mod is a modulus operation. Each of the plurality of QPP units is a parallel computation unit, and outputs in parallel a corresponding group of interleaver addresses, where ?(i) is also a ith interleaving address generated by the apparatus.Type: ApplicationFiled: September 28, 2010Publication date: February 23, 2012Applicants: NATIONAL CHIAO TUNG UNIVERSITY, INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: SHUENN-GI LEE, CHUNG HSUAN WANG, WERN-HO SHEEN
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Patent number: 8060796Abstract: A multiplexing method for data switching is disclosed. In the method, a continuous data is received, and the continuous data includes a plurality of super frames, and each super frame includes a plurality of frames. These super frames are divided into a set of even super frames and a set of odd super frames. The frames included in the set of odd super frames are sorted by corresponding required bit error rate of each frame decreasingly or increasingly. The frames included in the set of even super frames are sorted by the required bit error rate of each frame increasingly or decreasingly. An encoder is used to encode these sorted super frames.Type: GrantFiled: September 29, 2007Date of Patent: November 15, 2011Assignee: Industrial Technology Research InstituteInventors: Chung-Hsuan Wang, Shuenn-Gi Lee
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Publication number: 20110066914Abstract: An address generation apparatus for a quadratic permutation polynomial (QPP) interleaver is provided. It comprises a basic recursive unit, and L recursive units represented by first recursive unit up to Lth recursive units. The apparatus inputs a plurality of configurable parameters according to a QPP function ?(i)=(f1i+f2i2) mod k, generates a plurality of interleaver addresses in serial via the basic recursive unit, and generates L groups of corresponding interleaver addresses via the first up to the Lth recursive units, wherein ?(i) is the i-th interleaver address generated by the apparatus, f1 and f2 are QPP coefficients, and k is information block length of an input sequence, 0?i?k?1.Type: ApplicationFiled: December 25, 2009Publication date: March 17, 2011Inventors: Shuenn-Gi Lee, Chung-Hsuan Wang, Wern-Ho Sheen
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Publication number: 20090016352Abstract: A multiplexing method for data switching is disclosed. In the method, a continuous data is received, and the continuous data includes a plurality of super frames, and each super frame includes a plurality of frames. These super frames are divided into a set of even super frames and a set of odd super frames. The frames included in the set of odd super frames are sorted by corresponding required bit error rate of each frame decreasingly or increasingly. The frames included in the set of even super frames are sorted by the required bit error rate of each frame increasingly or decreasingly. An encoder is used to encode these sorted super frames.Type: ApplicationFiled: September 29, 2007Publication date: January 15, 2009Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, NATIONAL CHIAO TUNG UNIVERSITYInventors: Chung-Hsuan Wang, Shuenn-Gi Lee