Patents by Inventor Chung-Hsun Huang
Chung-Hsun Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240092662Abstract: A method for removing a heavy metal from water includes subjecting a microbial solution containing a liquid culture of a urease-producing bacterial strain and a reaction solution containing a manganese compound and urea to a microbial-induced precipitation reaction, so as to obtain biomineralized manganese carbonate (MnCO3) particles, admixing the biomineralized MnCO3 particles with water containing a heavy metal, so that the biomineralized MnCO3 particles adsorb the heavy metal in the water to form a precipitate, and removing the precipitate from the water.Type: ApplicationFiled: February 9, 2023Publication date: March 21, 2024Inventors: Chien-Yen CHEN, Yi-Hsun HUANG, Pin-Yun LIN, Anggraeni Kumala DEWI, Koyeli DAS, Uttara SUKUL, Tsung-Hsien CHEN, Raju Kumar SHARMA, Cheng-Kang LU, Chung-Ming LU
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Patent number: 11923315Abstract: Semiconductor package includes a pair of dies, a redistribution structure, and a conductive plate. Dies of the pair of dies are disposed side by side. Each die includes a contact pad. Redistribution structure is disposed on the pair of dies, and electrically connects the pair of dies. Redistribution structure includes an innermost dielectric layer, an outermost dielectric layer, and a redistribution conductive layer. Innermost dielectric layer is closer to the pair of dies. Redistribution conductive layer extends between the innermost dielectric layer and the outermost dielectric layer. Outermost dielectric layer is furthest from the pair of dies. Conductive plate is electrically connected to the contact pads of the pair of dies. Conductive plate extends over the outermost dielectric layer of the redistribution structure and over the pair of dies. Vertical projection of the conductive plate falls on spans of the dies of the pair of dies.Type: GrantFiled: July 12, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang, Wei-Ting Chen, Chien-Hsun Chen, Shih-Ya Huang
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Patent number: 11610996Abstract: A semiconductor structure and a method of forming the same are provided. In the semiconductor structure, contact spacers are formed at least on sidewalls of contact trenches in the substrate, so that the distance between the gate and the silicide layers disposed only on the bottom surfaces, rather than on the sidewalls and the bottom surfaces, of the contact trenches can be increased, and thus the current leakage induced by gate can be decreased.Type: GrantFiled: March 22, 2021Date of Patent: March 21, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Sheng-Fu Huang, Chung-Hsun Huang
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Publication number: 20210210638Abstract: A semiconductor structure and a method of forming the same are provided. In the semiconductor structure, contact spacers are formed at least on sidewalls of contact trenches in the substrate, so that the distance between the gate and the silicide layers disposed only on the bottom surfaces, rather than on the sidewalls and the bottom surfaces, of the contact trenches can be increased, and thus the current leakage induced by gate can be decreased.Type: ApplicationFiled: March 22, 2021Publication date: July 8, 2021Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Sheng-Fu Huang, Chung-Hsun Huang
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Patent number: 10991828Abstract: A semiconductor structure and a method of forming the same are provided. In the semiconductor structure, contact spacers are formed at least on sidewalls of contact trenches in the substrate, so that the distance between the gate and the silicide layers disposed only on the bottom surfaces, rather than on the sidewalls and the bottom surfaces, of the contact trenches can be increased, and thus the current leakage induced by gate can be decreased.Type: GrantFiled: March 20, 2019Date of Patent: April 27, 2021Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Sheng-Fu Huang, Chung-Hsun Huang
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Publication number: 20200303559Abstract: A semiconductor structure and a method of forming the same are provided. In the semiconductor structure, contact spacers are formed at least on sidewalls of contact trenches in the substrate, so that the distance between the gate and the silicide layers disposed only on the bottom surfaces, rather than on the sidewalls and the bottom surfaces, of the contact trenches can be increased, and thus the current leakage induced by gate can be decreased.Type: ApplicationFiled: March 20, 2019Publication date: September 24, 2020Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Sheng-Fu Huang, Chung-Hsun Huang
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Patent number: 9203310Abstract: A single-inductor multi-output (SIMO) conversion device for enlarging load range is disclosed. The SIMO conversion device comprises a power stage comprising a first switch and a second switch and receiving a direct-current (DC) current. A DC voltage source inputs the DC current to an inductor by timing of the first and second switches. Each control output circuit has a third switch connected with the inductor in series to receive an immediate current. The control output circuit sends out an output voltage selectively by the third switch. A control stage circuit receives a plurality of feedback voltage signals and selectively controls the order of adjusting energy of the output voltages by order control signals. The present invention uses a current sensing circuit to obtain the immediate current and switches control signals to establish the best order thereof according to different loads.Type: GrantFiled: December 31, 2013Date of Patent: December 1, 2015Assignee: NATIONAL CHUNG CHENG UNIVERSITYInventors: Chung-Hsun Huang, Chao-Chun Chen, Zhen-Yu Sun
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Patent number: 8981752Abstract: An energy-based oriented switching mode power supply includes a bi-directional converter having an energy input and a load output, and an energy based pulsed generator connected between the energy input and the load output for outputting a gate voltage signal controlling how much energy is supplied from the energy input. The energy based pulsed generator receives a clock signal and outputs the gate voltage signal according to the load output of the bi-directional converter when the clock signal is at a high level. Accordingly, the switching mode power supply achieves a hybrid of PWM and PFM, depending on the energy demand of the load output, for a fast transient response and a small voltage ripple whilst improving power efficiency over a wide load range.Type: GrantFiled: March 23, 2012Date of Patent: March 17, 2015Assignee: National Chung Cheng UniversityInventors: Chung-Hsun Huang, Chao-Chun Chen
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Publication number: 20150008742Abstract: A single-inductor multi-output (SIMO) conversion device for enlarging load range is disclosed. The SIMO conversion device comprises a power stage comprising a first switch and a second switch and receiving a direct-current (DC) current. A DC voltage source inputs the DC current to an inductor by timing of the first and second switches. Each control output circuit has a third switch connected with the inductor in series to receive an immediate current. The control output circuit sends out an output voltage selectively by the third switch. A control stage circuit receives a plurality of feedback voltage signals and selectively controls the order of adjusting energy of the output voltages by order control signals. The present invention uses a current sensing circuit to obtain the immediate current and switches control signals to establish the best order thereof according to different loads.Type: ApplicationFiled: December 31, 2013Publication date: January 8, 2015Applicant: National Chung Cheng UniversityInventors: Chung-Hsun HUANG, Chao-Chun CHEN, Zhen-Yu SUN
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Patent number: 8648582Abstract: The present invention provides a programmable low dropout linear regulator using a reference voltage to convert an input voltage into a regulated voltage according to a control signal. The programmable low dropout linear regulator includes an operational amplifier having a negative input coupled to receive the reference voltage, a first transistor having a gate coupled to an output terminal of the operational amplifier and a first source/drain coupled to an output terminal of the regulated voltage, a first impedance coupled between a positive input of the operational amplifier and the output terminal of the regulated voltage, and a second impedance coupled between the positive input of the operational amplifier and a ground. The second impedance includes a second transistor having a gate coupled to receive the control signal.Type: GrantFiled: December 27, 2010Date of Patent: February 11, 2014Assignee: National Chung Cheng UniversityInventors: Chung-Hsun Huang, Ke-Ming Su
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Publication number: 20130162237Abstract: An energy-based oriented switching mode power supply includes a bi-directional converter having an energy input and a load output, and an energy based pulsed generator connected between the energy input and the load output for outputting a gate voltage signal controlling how much energy is supplied from the energy input. The energy based pulsed generator receives a clock signal and outputs the gate voltage signal according to the load output of the bi-directional converter when the clock signal is at a high level. Accordingly, the switching mode power supply achieves a hybrid of PWM and PFM, depending on the energy demand of the load output, for a fast transient response and a small voltage ripple whilst improving power efficiency over a wide load range.Type: ApplicationFiled: March 23, 2012Publication date: June 27, 2013Inventors: Chung-Hsun Huang, Chao-Chun Chen
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Patent number: 8269805Abstract: An image processing module with less line buffers is provided. The image processing module receives an original image signal to drive a display panel. The image processing module includes a timing controller and a scaler. The timing controller includes a line buffer and a control unit. The line buffer registers the original image signal and outputs a storage image signal. The scaler receives the storage image signal, adjusts the resolution of the storage image signal, and outputs a scaled image signal to the control unit according to the resolution of the storage image signal. The control unit receives the scaled image signal and outputs a display signal to drive the display panel according to the scaled image signal.Type: GrantFiled: December 8, 2005Date of Patent: September 18, 2012Assignee: Himax Technologies LimitedInventors: Chung-Hsun Huang, Kuei-Hsiang Chen
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Publication number: 20120105047Abstract: The present invention provides a programmable low dropout linear regulator using a reference voltage to convert an input voltage into a regulated voltage according to a control signal. The programmable low dropout linear regulator includes an operational amplifier having a negative input coupled to receive the reference voltage, a first transistor having a gate coupled to an output terminal of the operational amplifier and a first source/drain coupled to an output terminal of the regulated voltage, a first impedance coupled between a positive input of the operational amplifier and the output terminal of the regulated voltage, and a second impedance coupled between the positive input of the operational amplifier and a ground. The second impedance includes a second transistor having a gate coupled to receive the control signal.Type: ApplicationFiled: December 27, 2010Publication date: May 3, 2012Applicant: NATIONAL CHUNG CHENG UNIVERSITYInventors: CHUNG-HSUN HUANG, KE-MING SU
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Patent number: 8144170Abstract: An apparatus for outputting an image by scaling an original image to a different size is disclosed. The apparatus includes an interpolator and at least one line buffer. The interpolator generates lines of the output image, at least one of which is derived by interpolation of lines of the original image, and the line buffer temporally stores pixels on a same one of the lines of the original image for the interpolation, in which the line buffer has single-port memories and each of the single-port memories is accessed for reading and writing values of the pixels which are non-adjacent to one another. A line buffer is also disclosed herein.Type: GrantFiled: March 28, 2007Date of Patent: March 27, 2012Assignee: Himax Technologies LimitedInventor: Chung-Hsun Huang
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Patent number: 7800637Abstract: An overdrive gray level data modifier and method of looking up thereof are provided. The overdrive data modifier obtains and outputs overdrive gray level data according to several overdrive gray values corresponding to several previous gray level index values and several current gray level index values. The overdrive data modifier includes a first, a second, a third and a fourth memory unit. The overdrive gray values are respectively stored in the first, the second, the third and the fourth memory unit. Firstly, a previous gray level index value and a current gray level index value are compared according to a current frame gray level data and a previous frame gray level data, and at least a corresponding overdrive gray level data are obtained from the overdrive gray value. At last, the overdrive gray level data are obtained according to the corresponding overdrive gray level data.Type: GrantFiled: January 10, 2006Date of Patent: September 21, 2010Assignee: Himax Technologies LimitedInventors: Chung-Hsun Huang, Pen-Hsin Chen
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Patent number: 7764256Abstract: An apparatus for overdrive computation and method therefor. The overdrive computation apparatus is used for generating a desired overdrive gray-level value and includes first and second addition/subtraction devices, a priority encoder, and a computation device. The first addition/subtraction device outputs a difference value indicating difference between a first overdrive gray-level value OD1 and a second overdrive gray-level value OD2. The priority encoder determines a decision signal according to the difference value. The computation device receives first gray-level data, determines a first computation according to the decision signal, and performs the first computation on the first gray-level data to output operated gray-level data. The first gray-level data indicates a value lying between the ith first gray-level index value X(i) and the (i+1)th first gray-level index value X(i+1).Type: GrantFiled: January 5, 2006Date of Patent: July 27, 2010Assignee: Himax Technologies LimitedInventors: Chung-Hsun Huang, Fung-Jane Chang
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Publication number: 20080266461Abstract: A video processing circuit with multiple-interface has a multiple-interface device, a timing controller, and a register. The timing controller is capable of sequencing and transmitting a signal of a low voltage differential signal, a reduced swing differential signal type or a transistor-transistor logic signal type to the multiple-interface device. The register sets the multiple-interface device to be adapted to output the signals of the types to a source driver.Type: ApplicationFiled: April 27, 2007Publication date: October 30, 2008Applicant: HIMAX TECHNOLOGIES LIMITEDInventors: Chung-Hsun Huang, Kuei-Hsiang Chen
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Publication number: 20080238943Abstract: An apparatus for outputting an image by scaling an original image to a different size is disclosed. The apparatus includes an interpolator and at least one line buffer. The interpolator generates lines of the output image, at least one of which is derived by interpolation of lines of the original image, and the line buffer temporally stores pixels on a same one of the lines of the original image for the interpolation, in which the line buffer has single-port memories and each of the single-port memories is accessed for reading and writing values of the pixels which are non-adjacent to one another. A line buffer is also disclosed herein.Type: ApplicationFiled: March 28, 2007Publication date: October 2, 2008Applicant: HIMAX TECHNOLOGIES LIMITEDInventor: Chung-Hsun HUANG
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Publication number: 20070146479Abstract: A control chipset for a video display apparatus is provided. The control chipset is coupled to a frame buffer and a display unit. The control chipset comprises: a scaler for receiving and processing an input video signal to generate a scaled video signal; a three-dimensional (3D) video enhancing unit for receiving and processing the scaled video signal to generate an enhanced video signal; an overdrive unit for receiving and processing the enhanced video signal to generate an overdriven video signal; a timing controller for generating a timing control signal, receiving the overdriven video signal, and transferring the timing control signal and the overdriven video signal to the display unit; and a memory controller. The scaler, the 3D video enhancing unit, and the overdriven unit access the frame buffer through the same memory controller, and data accessed by the overdrive unit is compressed.Type: ApplicationFiled: March 10, 2006Publication date: June 28, 2007Inventors: Chen-Jen Huang, Chung-Hsun Huang, Kuei-Hsiang Chen
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Patent number: 7206007Abstract: A method for video processing which provides a scaled image using two different clock frequencies is provided. The method receives source pixel data using a first clock signal and scales the source pixel data to destination pixel data. After that, the destination pixel data is provided using a second clock signal having a second clock frequency and a third clock signal having a third clock frequency during blanking period and active period, respectively.Type: GrantFiled: February 4, 2005Date of Patent: April 17, 2007Assignee: Himax Technologies, Inc.Inventors: Chung-Hsun Huang, Yuan-Kai Chu, Kuei-Hsiang Chen