Patents by Inventor Chung-Hsun LI

Chung-Hsun LI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220171299
    Abstract: A method of determining an overlay value of a substrate, the method including: obtaining temperature data that includes data on measured temperature at one or more positions on a substrate table after a substrate has been loaded onto the substrate table; and determining an overlay value of the substrate in dependence on the obtained temperature data. There is further disclosed a method of determining a performance of a clamping by a substrate table using a determined overlay value.
    Type: Application
    Filed: January 17, 2020
    Publication date: June 2, 2022
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Ruud Hendrikus Martinus Johannes BLOKS, Hendrik Cornelis Anton BORGER, Frederik Eduard DE JONG, Johan Gertrudis Cornelis KUNNEN, Siebe LANDHEER, Chung-Hsun LI, Patricius Jacobus NEEFS, Georgios TSIROGIANNIS, Si-Han ZENG
  • Publication number: 20220082949
    Abstract: A method for categorizing a substrate subject to a semiconductor manufacturing process including multiple operations, the method including: obtaining values of functional indicators derived from data generated during one or more of the multiple operations on the substrate, the functional indicators characterizing at least one operation; applying a decision model including one or more threshold values to the values of the functional indicators to obtain one or more categorical indicators; and assigning a category to the substrate based on the one or more categorical indicators.
    Type: Application
    Filed: January 9, 2020
    Publication date: March 17, 2022
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Arnaud HUBAUX, Johan Franciscus Maria BECKERS, Dylan John David DAVIES, Johan Gertrudis Cornelis KUNNEN, Willem Richard PONGERS, Ajinkya Ravindra DAWARE, Chung-Hsun LI, Georgios TSIROGIANNIS, Hendrik Cornelis Anton BORGER, Frederik Eduard DEJONG, Juan Manuel GONZALEZ HUESCA, Andriy HLOD, Maxim PISARENCO
  • Publication number: 20210215622
    Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked to at least partially recompose the measurement results according to the sample plan.
    Type: Application
    Filed: March 8, 2021
    Publication date: July 15, 2021
    Applicant: ASML Netherlands B.V.
    Inventors: Wouter Lodewijk Elings, Franciscus Bernardus Maria Van Bilsen, Christianus Gerardus Maria De Mol, Everhardus Cornelis Mos, Hoite Pieter Theodoor Tolsma, Peter Ten Berge, Paul Jacques Van Wijnen, Leonardus Henricus Marie Verstappen, Gerald Dicker, Reiner Maria Jungblut, Chung-Hsun Li
  • Patent number: 10996176
    Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked to at least partially recompose the measurement results according to the sample plan.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: May 4, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Wouter Lodewijk Elings, Franciscus Bernardus Maria Van Bilsen, Christianus Gerardus Maria De Mol, Everhardus Cornelis Mos, Hoite Pieter Theodoor Tolsma, Peter Ten Berge, Paul Jacques Van Wijnen, Leonardus Henricus Marie Verstappen, Gerald Dicker, Reiner Maria Jungblut, Chung-Hsun Li
  • Publication number: 20200319118
    Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked to at least partially recompose the measurement results according to the sample plan.
    Type: Application
    Filed: June 18, 2020
    Publication date: October 8, 2020
    Applicant: ASML Netherlands B.V.
    Inventors: Wouter Lodewijk ELINGS, Franciscus Bernardus Maria VAN BILSEN, Christianus Gerardus Maria DE MOL, Everhardus Cornelis MOS, Hoite Pieter Theodoor TOLSMA, Peter TEN BERGE, Paul Jacques VAN WIJNEN, Leonard us Henricus Marie VERSTAPPEN, Gerald DICKER, Reiner Maria JUNGBLUT, Chung-Hsun LI
  • Patent number: 10746668
    Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced 2506 defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used 2508 to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked 2510 to at least partially recompose the measurement results according to the sample plan.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: August 18, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Wouter Lodewijk Elings, Franciscus Bernardus Maria Van Bilsen, Christianus Gerardus Maria De Mol, Everhardus Cornelis Mos, Hoite Pieter Theodoor Tolsma, Peter Ten Berge, Paul Jacques Van Wijnen, Leonardus Henricus Marie Verstappen, Gerald Dicker, Reiner Maria Jungblut, Chung-Hsun Li
  • Publication number: 20190384164
    Abstract: A method for mitigating an effect of non-uniform pellicle degradation on control of a substrate patterning process and an associated lithographic apparatus. The method includes quantifying an effect of the non-uniform pellicle degradation on one or more properties of patterned features, such as one or more metrology targets, formed on the substrate by the substrate patterning process. A process control correction is then determined based on the quantification of the effect of the non-uniform pellicle degradation.
    Type: Application
    Filed: February 16, 2018
    Publication date: December 19, 2019
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Marcel Theodorus Maria VAN KESSEL, Frederik Eduard DE JONG, Cornelis Melchior BROUWER, Kevin VAN DE RUIT, Chung-Hsun LI
  • Publication number: 20190301850
    Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced 2506 defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used 2508 to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked 2510 to at least partially recompose the measurement results according to the sample plan.
    Type: Application
    Filed: April 10, 2019
    Publication date: October 3, 2019
    Applicant: ASML Netherlands B.V.
    Inventors: Wouter Lodewijk ELINGS, Franciscus Bernardus Maria Van Bilsen, Christianus Gerardus Maria De Mol, Everhardus Cornelis Mos, Hoite Pieter Theodoor Tolsma, Peter Ten Berge, Paul Jacques Van Wijnen, Leonardus Henricus Marie Verstappen, Gerald Dicker, Reiner Maria Jungblut, Chung-Hsun Li
  • Patent number: 10317191
    Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced 2506 defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used 2508 to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked 2510 to at least partially recompose the measurement results according to the sample plan.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: June 11, 2019
    Assignee: ASML Netherlands B.V.
    Inventors: Wouter Lodewijk Elings, Franciscus Bernardus Maria Van Bilsen, Christianus Gerardus Maria De Mol, Everhardus Cornelis Mos, Hoite Pieter Theodoor Tolsma, Peter Ten Berge, Paul Jacques Van Wijnen, Leonardus Henricus Marie Verstappen, Gerald Dicker, Reiner Maria Jungblut, Chung-Hsun Li
  • Publication number: 20110273685
    Abstract: A method of production of alignment marks uses a self-aligned double patterning process. An alignment mark pattern is provided with first and second sub-segmented elements. After selecting the dipolar illumination orientation, dipole-X is used to illuminate the pattern and to image the first elements on the wafer, but not the second elements. Alternatively, dipole-Y is used to illuminate the pattern and to image the second elements on the wafer, but not the first elements. In either case, self-aligned double patterning processing may then be performed to produce product-like alignment marks with high contrast and wafer quality (WQ). Subsequently the X and Y alignment marks thus produced are used for the step of alignment in a lithographic process.
    Type: Application
    Filed: March 30, 2011
    Publication date: November 10, 2011
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Chung-Hsun LI, Richard Johannes Franciscus Van Haren, Sami Musa, David Deckers, Shun-Der Wu