Patents by Inventor Chung-Hsun LI
Chung-Hsun LI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11977034Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked to at least partially recompose the measurement results according to the sample plan.Type: GrantFiled: March 8, 2021Date of Patent: May 7, 2024Assignee: ASML Netherlands B.V.Inventors: Wouter Lodewijk Elings, Franciscus Bernardus Maria Van Bilsen, Christianus Gerardus Maria De Mol, Everhardus Cornelis Mos, Hoite Pieter Theodoor Tolsma, Peter Ten Berge, Paul Jacques Van Wijnen, Leonardus Henricus Marie Verstappen, Gerald Dicker, Reiner Maria Jungblut, Chung-Hsun Li
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Publication number: 20240088148Abstract: A semiconductor device includes a substrate, a stack of semiconductor nanosheets, a dielectric wall, and a gate structure. The substrate includes a nanosheet mesa, and the stack of semiconductor nanosheets is disposed on the nanosheet mesa. The dielectric wall crosses through the nanosheet mesa and the stack of semiconductor nanosheets. The gate structure wraps the stack of semiconductor nanosheets and crosses over the dielectric wall, wherein a top of the dielectric wall has a recess.Type: ApplicationFiled: January 11, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Ren Chen, Chung-Ting Li, Shih-Hsun Chang
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Publication number: 20230341783Abstract: A method of determining matching performance between tools used in semiconductor manufacture and associated tools is described. The method includes obtaining a plurality of data sets related to a plurality of tools and a representation of the data sets in a reduced space having a reduced dimensionality. A matching metric and/or matching correction is determined based on matching the reduced data sets in the reduced space.Type: ApplicationFiled: January 19, 2021Publication date: October 26, 2023Applicant: ASML NETHERLANDS B.V.Inventors: Arnaud HUBAUX, Patrick WARNAAR, Scott Anderson MIDDLEBROOKS, Tijmen Pieter COLLIGNON, Chung-Hsun LI, Georgios TSIROGIANNIS, Sayyed Mojtaba SHAKERI
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Publication number: 20230333482Abstract: A method for categorizing a substrate subject to a semiconductor manufacturing process including multiple operations, the method including: obtaining values of functional indicators derived from data generated during one or more of the multiple operations on the substrate, the functional indicators characterizing at least one operation; applying a decision model including one or more threshold values to the values of the functional indicators to obtain one or more categorical indicators; and assigning a category to the substrate based on the one or more categorical indicators.Type: ApplicationFiled: June 21, 2023Publication date: October 19, 2023Applicant: ASML NETHERLANDS B.V.Inventors: Arnaud HUBAUX, Johan Franciscus Maria Beckers, Dylan John David Davies, Johan Gertrudis Cornelis Kunnen, Willem Richard Pongers, Ajinkya Ravindra Daware, Chung-Hsun Li, Georgios Tsirogiannis, Hendrik Cornelis Anton Borger, Frederik Eduard De Jong, Juan Manuel Gonzalez Huesca, Andriy Hlod, Maxim Pisarenco
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Patent number: 11774869Abstract: A method of determining an overlay value of a substrate, the method including: obtaining temperature data that includes data on measured temperature at one or more positions on a substrate table after a substrate has been loaded onto the substrate table; and determining an overlay value of the substrate in dependence on the obtained temperature data. There is further disclosed a method of determining a performance of a clamping by a substrate table using a determined overlay value.Type: GrantFiled: January 17, 2020Date of Patent: October 3, 2023Assignee: ASML NETHERLANDS B.V.Inventors: Ruud Hendrikus Martinus Johannes Bloks, Hendrik Cornelis Anton Borger, Frederik Eduard De Jong, Johan Gertrudis Cornelis Kunnen, Siebe Landheer, Chung-Hsun Li, Patricius Jacobus Neefs, Georgios Tsirogiannis, Si-Han Zeng
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Patent number: 11774861Abstract: Disclosed is a method of determining calibrated reference exposure and measure grids for referencing position of a substrate stage in a lithographic system. The method comprises obtaining calibration data relating to one or more calibration substrates; and determining an exposure grid for an exposure side of the lithographic system from said calibration data and a measure grid for a measure side of the lithographic system from said calibration data. The exposure grid and said measure grid are decomposed so as to remove a calibration substrate dependent component from said exposure grid and from said measure grid to obtain a substrate independent exposure grid and substrate independent measure grid.Type: GrantFiled: October 12, 2020Date of Patent: October 3, 2023Assignee: ASML Netherlands B.V.Inventors: Cornelis Melchior Brouwer, Chung-Hsun Li
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Patent number: 11687007Abstract: A method for categorizing a substrate subject to a semiconductor manufacturing process including multiple operations, the method including: obtaining values of functional indicators derived from data generated during one or more of the multiple operations on the substrate, the functional indicators characterizing at least one operation; applying a decision model including one or more threshold values to the values of the functional indicators to obtain one or more categorical indicators; and assigning a category to the substrate based on the one or more categorical indicators.Type: GrantFiled: January 9, 2020Date of Patent: June 27, 2023Assignee: ASML NETHERLANDS B.V.Inventors: Arnaud Hubaux, Johan Franciscus Maria Beckers, Dylan John David Davies, Johan Gertrudis Cornelis Kunnen, Willem Richard Pongers, Ajinkya Ravindra Daware, Chung-Hsun Li, Georgios Tsirogiannis, Hendrik Cornelis Anton Borger, Frederik Eduard De Jong, Juan Manuel Gonzalez Huesca, Andriy Hlod, Maxim Pisarenco
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Publication number: 20220390855Abstract: Disclosed is a method of determining calibrated reference exposure and measure grids for referencing position of a substrate stage in a lithographic system. The method comprises obtaining calibration data relating to one or more calibration substrates; and determining an exposure grid for an exposure side of the lithographic system from said calibration data and a measure grid for a measure side of the lithographic system from said calibration data. The exposure grid and said measure grid are decomposed so as to remove a calibration substrate dependent component from said exposure grid and from said measure grid to obtain a substrate independent exposure grid and substrate independent measure grid.Type: ApplicationFiled: October 12, 2020Publication date: December 8, 2022Applicant: ASML Netherlands B.V.Inventors: Cornelis Melchior BROUWER, Chung-Hsun LI
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Publication number: 20220171299Abstract: A method of determining an overlay value of a substrate, the method including: obtaining temperature data that includes data on measured temperature at one or more positions on a substrate table after a substrate has been loaded onto the substrate table; and determining an overlay value of the substrate in dependence on the obtained temperature data. There is further disclosed a method of determining a performance of a clamping by a substrate table using a determined overlay value.Type: ApplicationFiled: January 17, 2020Publication date: June 2, 2022Applicant: ASML NETHERLANDS B.V.Inventors: Ruud Hendrikus Martinus Johannes BLOKS, Hendrik Cornelis Anton BORGER, Frederik Eduard DE JONG, Johan Gertrudis Cornelis KUNNEN, Siebe LANDHEER, Chung-Hsun LI, Patricius Jacobus NEEFS, Georgios TSIROGIANNIS, Si-Han ZENG
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Publication number: 20220082949Abstract: A method for categorizing a substrate subject to a semiconductor manufacturing process including multiple operations, the method including: obtaining values of functional indicators derived from data generated during one or more of the multiple operations on the substrate, the functional indicators characterizing at least one operation; applying a decision model including one or more threshold values to the values of the functional indicators to obtain one or more categorical indicators; and assigning a category to the substrate based on the one or more categorical indicators.Type: ApplicationFiled: January 9, 2020Publication date: March 17, 2022Applicant: ASML NETHERLANDS B.V.Inventors: Arnaud HUBAUX, Johan Franciscus Maria BECKERS, Dylan John David DAVIES, Johan Gertrudis Cornelis KUNNEN, Willem Richard PONGERS, Ajinkya Ravindra DAWARE, Chung-Hsun LI, Georgios TSIROGIANNIS, Hendrik Cornelis Anton BORGER, Frederik Eduard DEJONG, Juan Manuel GONZALEZ HUESCA, Andriy HLOD, Maxim PISARENCO
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Publication number: 20210215622Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked to at least partially recompose the measurement results according to the sample plan.Type: ApplicationFiled: March 8, 2021Publication date: July 15, 2021Applicant: ASML Netherlands B.V.Inventors: Wouter Lodewijk Elings, Franciscus Bernardus Maria Van Bilsen, Christianus Gerardus Maria De Mol, Everhardus Cornelis Mos, Hoite Pieter Theodoor Tolsma, Peter Ten Berge, Paul Jacques Van Wijnen, Leonardus Henricus Marie Verstappen, Gerald Dicker, Reiner Maria Jungblut, Chung-Hsun Li
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Patent number: 10996176Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked to at least partially recompose the measurement results according to the sample plan.Type: GrantFiled: June 18, 2020Date of Patent: May 4, 2021Assignee: ASML Netherlands B.V.Inventors: Wouter Lodewijk Elings, Franciscus Bernardus Maria Van Bilsen, Christianus Gerardus Maria De Mol, Everhardus Cornelis Mos, Hoite Pieter Theodoor Tolsma, Peter Ten Berge, Paul Jacques Van Wijnen, Leonardus Henricus Marie Verstappen, Gerald Dicker, Reiner Maria Jungblut, Chung-Hsun Li
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Publication number: 20200319118Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked to at least partially recompose the measurement results according to the sample plan.Type: ApplicationFiled: June 18, 2020Publication date: October 8, 2020Applicant: ASML Netherlands B.V.Inventors: Wouter Lodewijk ELINGS, Franciscus Bernardus Maria VAN BILSEN, Christianus Gerardus Maria DE MOL, Everhardus Cornelis MOS, Hoite Pieter Theodoor TOLSMA, Peter TEN BERGE, Paul Jacques VAN WIJNEN, Leonard us Henricus Marie VERSTAPPEN, Gerald DICKER, Reiner Maria JUNGBLUT, Chung-Hsun LI
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Patent number: 10746668Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced 2506 defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used 2508 to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked 2510 to at least partially recompose the measurement results according to the sample plan.Type: GrantFiled: April 10, 2019Date of Patent: August 18, 2020Assignee: ASML Netherlands B.V.Inventors: Wouter Lodewijk Elings, Franciscus Bernardus Maria Van Bilsen, Christianus Gerardus Maria De Mol, Everhardus Cornelis Mos, Hoite Pieter Theodoor Tolsma, Peter Ten Berge, Paul Jacques Van Wijnen, Leonardus Henricus Marie Verstappen, Gerald Dicker, Reiner Maria Jungblut, Chung-Hsun Li
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Publication number: 20190384164Abstract: A method for mitigating an effect of non-uniform pellicle degradation on control of a substrate patterning process and an associated lithographic apparatus. The method includes quantifying an effect of the non-uniform pellicle degradation on one or more properties of patterned features, such as one or more metrology targets, formed on the substrate by the substrate patterning process. A process control correction is then determined based on the quantification of the effect of the non-uniform pellicle degradation.Type: ApplicationFiled: February 16, 2018Publication date: December 19, 2019Applicant: ASML NETHERLANDS B.V.Inventors: Marcel Theodorus Maria VAN KESSEL, Frederik Eduard DE JONG, Cornelis Melchior BROUWER, Kevin VAN DE RUIT, Chung-Hsun LI
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Publication number: 20190301850Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced 2506 defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used 2508 to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked 2510 to at least partially recompose the measurement results according to the sample plan.Type: ApplicationFiled: April 10, 2019Publication date: October 3, 2019Applicant: ASML Netherlands B.V.Inventors: Wouter Lodewijk ELINGS, Franciscus Bernardus Maria Van Bilsen, Christianus Gerardus Maria De Mol, Everhardus Cornelis Mos, Hoite Pieter Theodoor Tolsma, Peter Ten Berge, Paul Jacques Van Wijnen, Leonardus Henricus Marie Verstappen, Gerald Dicker, Reiner Maria Jungblut, Chung-Hsun Li
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Patent number: 10317191Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced 2506 defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used 2508 to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked 2510 to at least partially recompose the measurement results according to the sample plan.Type: GrantFiled: February 14, 2017Date of Patent: June 11, 2019Assignee: ASML Netherlands B.V.Inventors: Wouter Lodewijk Elings, Franciscus Bernardus Maria Van Bilsen, Christianus Gerardus Maria De Mol, Everhardus Cornelis Mos, Hoite Pieter Theodoor Tolsma, Peter Ten Berge, Paul Jacques Van Wijnen, Leonardus Henricus Marie Verstappen, Gerald Dicker, Reiner Maria Jungblut, Chung-Hsun Li
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Publication number: 20110273685Abstract: A method of production of alignment marks uses a self-aligned double patterning process. An alignment mark pattern is provided with first and second sub-segmented elements. After selecting the dipolar illumination orientation, dipole-X is used to illuminate the pattern and to image the first elements on the wafer, but not the second elements. Alternatively, dipole-Y is used to illuminate the pattern and to image the second elements on the wafer, but not the first elements. In either case, self-aligned double patterning processing may then be performed to produce product-like alignment marks with high contrast and wafer quality (WQ). Subsequently the X and Y alignment marks thus produced are used for the step of alignment in a lithographic process.Type: ApplicationFiled: March 30, 2011Publication date: November 10, 2011Applicant: ASML NETHERLANDS B.V.Inventors: Chung-Hsun LI, Richard Johannes Franciscus Van Haren, Sami Musa, David Deckers, Shun-Der Wu