Patents by Inventor Chung-Hua WENG

Chung-Hua WENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240152880
    Abstract: A multi-channel payment method for a multi-channel payment system comprises the payer or the payee who initiated the payment request logs in to the multi-channel payment system; the payer or the payee who initiated the payment request placing an order in the multi-channel payment system, wherein the order comprises a designated payment gateway; the multi-channel payment system determining a predicted fee of the order according to the designated payment gateway, past order records, and a real-time exchange rate; the multi-channel payment system performing an anti-money laundering verification of the order; the payer reviewing the order and the predicted fee through a multiple auditing method; and the multi-channel payment system executing payment from the payer to the payee according to the order and the designated payment gateway, and storing a payment detail of the order.
    Type: Application
    Filed: February 13, 2023
    Publication date: May 9, 2024
    Applicant: OBOOK INC.
    Inventors: Chun-Kai Wang, Chung-Han Hsieh, Chun-Jen Chen, Po-Hua Lin, Wei-Te Lin, Pei-Hsuan Weng, Mei-Su Wang, I-Cheng Lin, Cheng-Wei Chen
  • Patent number: 11955460
    Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Da Tsai, Meng-Tse Chen, Sheng-Feng Weng, Sheng-Hsiang Chiu, Wei-Hung Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
  • Patent number: 11953740
    Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
  • Patent number: 11947173
    Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
  • Publication number: 20240076422
    Abstract: A supported metallocene catalyst includes a carrier and a metallocene component. The carrier includes an inorganic oxide particle and an alkyl aluminoxane material. The inorganic oxide particle includes at least one inorganic oxide compound selected from the group consisting of an oxide of Group 3A and an oxide of Group 4A. The alkyl aluminoxane material includes an alkyl aluminoxane compound and an alkyl aluminum compound that is present in amount ranging from greater than 0.01 wt % to less than 14 wt % base on 100 wt % of the alkyl aluminoxane material. The metallocene component is supported on the carrier, and includes one of a metallocene compound containing a metal from Group 3B, a metallocene compound containing a metal from Group 4B, and a combination thereof. A method for preparing the supported metallocene catalyst and a method for preparing polyolefin using the supported metallocene catalyst are also disclosed.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 7, 2024
    Inventors: Jing-Cherng TSAI, Jen-Long WU, Wen-Hao KANG, Kuei-Pin LIN, Jing-Yu LEE, Jun-Ye HONG, Zih-Yu SHIH, Cheng-Hung CHIANG, Gang-Wei SHEN, Yu-Chuan SUNG, Chung-Hua WENG, Hsing-Ya CHEN
  • Publication number: 20240069277
    Abstract: A semiconductor package includes a first die stack structure and a second die stack structure, an insulating encapsulation, a redistribution structure, at least one prism structure and at least one reflector. The first die stack structure and the second die stack structure are laterally spaced apart from each other along a first direction, and each of the first die stack structure and the second die stack structure comprises an electronic die; and a photonic die electronically communicating with the electronic die. The insulating encapsulation laterally encapsulates the first die stack structure and the second die stack structure. The redistribution structure is disposed on the first die stack structure, the second die stack structure and the insulating encapsulation, and electrically connected to the first die stack structure and the second die stack structure. The at least one prism structure is disposed within the redistribution structure and optically coupled to the photonic die.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Yi Kuo, Chen-Hua Yu, Cheng-Chieh Hsieh, Che-Hsiang Hsu, Chung-Ming Weng, Tsung-Yuan Yu