Patents by Inventor Chung-Hua Yu

Chung-Hua Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210375770
    Abstract: A manufacturing method of a semiconductor package is provided. The method includes: providing an initial rigid-flexible substrate, wherein the initial rigid-flexible substrate includes rigid structures and a flexible core laterally penetrating through the rigid structures, and further includes a supporting frame connected to the rigid structures; bonding a package structure onto the initial rigid-flexible substrate, wherein the package structure includes semiconductor dies and an encapsulant laterally surrounding the semiconductor dies; and removing the supporting frame.
    Type: Application
    Filed: August 13, 2021
    Publication date: December 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chen-Hua Yu, Chung-Shi Liu, Chih-Yuan Chang, Jiun-Yi Wu, Jeng-Shien Hsieh, Tin-Hao Kuo
  • Publication number: 20210366877
    Abstract: A structure includes core substrates attached to a first side of a redistribution structure, wherein the first redistribution structure includes first conductive features and first dielectric layers, wherein each core substrate includes conductive pillars, wherein the conductive pillars of the core substrates physically and electrically contact first conductive features; an encapsulant extending over the first side of the redistribution structure, wherein the encapsulant extends along sidewalls of each core substrate; and an integrated device package connected to a second side of the first redistribution structure.
    Type: Application
    Filed: January 7, 2021
    Publication date: November 25, 2021
    Inventors: Jiun Yi Wu, Chen-Hua Yu, Chung-Shi Liu
  • Publication number: 20210366872
    Abstract: A semiconductor device, a circuit board structure and a manufacturing forming thereof are provided. A circuit board structure includes a core layer, a first build-up layer and a second build-up layer. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The circuit board structure has a plurality of stress releasing trenches extending into the first build-up layer and the second build-up layer.
    Type: Application
    Filed: August 9, 2021
    Publication date: November 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tin-Hao Kuo, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Yu-Chia Lai, Po-Yuan Teng
  • Patent number: 11183487
    Abstract: A packaged semiconductor device including an integrated passive device-containing package component disposed between a power module and an integrated circuit-containing package and a method of forming the same are disclosed. In an embodiment, a device includes a first package component including a first integrated circuit die; a first encapsulant at least partially surrounding the first integrated circuit die; and a redistribution structure on the first encapsulant and coupled to the first integrated circuit die; a second package component bonded to the first package component, the second package component including an integrated passive device; and a second encapsulant at least partially surrounding the integrated passive device; and a power module attached to the first package component through the second package component.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: November 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Hui Lai, Shu-Rong Chun, Kuo-Lung Pan, Tin Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu, Yu-Chia Lai
  • Patent number: 11171088
    Abstract: An electronic apparatus is provided. The electronic apparatus includes an integrated fan-out package, a dielectric housing, and a plurality of conductive patterns. The dielectric housing is covering the integrated fan-out package, wherein a gap or a first dielectric layer is in between the dielectric housing and the integrated fan-out package. The plurality of conductive patterns is located on a surface of the dielectric housing, wherein the plurality of conductive patterns is located in between the dielectric housing and the integrated fan-out package.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: November 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Chun Tang, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang, Che-Wei Hsu
  • Patent number: 11171090
    Abstract: A method includes forming a device structure, the method including forming a first redistribution structure over and electrically connected to a semiconductor device, forming a molding material surrounding the first redistribution structure and the semiconductor device, forming a second redistribution structure over the molding material and the first redistribution structure, the second redistribution structure electrically connected to the first redistribution structure, attaching an interconnect structure to the second redistribution structure, the interconnect structure including a core substrate, the interconnect structure electrically connected to the second redistribution structure, forming an underfill material on sidewalls of the interconnect structure and between the second redistribution structure and the interconnect structure.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: November 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun Yi Wu, Ching-Hua Hsieh, Chen-Hua Yu, Chung-Shi Liu, Shou-Yi Wang, Chien-Hsun Chen
  • Publication number: 20210343651
    Abstract: Semiconductor package includes a pair of dies, a redistribution structure, and a conductive plate. Dies of the pair of dies are disposed side by side. Each die includes a contact pad. Redistribution structure is disposed on the pair of dies, and electrically connects the pair of dies. Redistribution structure includes an innermost dielectric layer, an outermost dielectric layer, and a redistribution conductive layer. Innermost dielectric layer is closer to the pair of dies. Redistribution conductive layer extends between the innermost dielectric layer and the outermost dielectric layer. Outermost dielectric layer is furthest from the pair of dies. Conductive plate is electrically connected to the contact pads of the pair of dies. Conductive plate extends over the outermost dielectric layer of the redistribution structure and over the pair of dies. Vertical projection of the conductive plate falls on spans of the dies of the pair of dies.
    Type: Application
    Filed: July 12, 2021
    Publication date: November 4, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang, Wei-Ting Chen, Chien-Hsun Chen, Shih-Ya Huang
  • Publication number: 20210335713
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad.
    Type: Application
    Filed: September 4, 2020
    Publication date: October 28, 2021
    Inventors: Xin-Hua Huang, Chung-Yi Yu, Kuei-Ming Chen
  • Publication number: 20210335726
    Abstract: In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a
    Type: Application
    Filed: July 17, 2020
    Publication date: October 28, 2021
    Inventors: Jiun Yi Wu, Chen-Hua Yu, Chung-Shi Liu
  • Patent number: 11152323
    Abstract: Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, and an external connector on the connector support metallization. The redistribution structure includes a dielectric layer disposed distally from the encapsulant and the integrated circuit die. The connector support metallization has a first portion on a surface of the dielectric layer and has a second portion extending in an opening through the dielectric layer. The first portion of the connector support metallization has a sloped sidewall extending in a direction away from the surface of the dielectric layer.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chien-Yu Li, Hung-Jui Kuo, Li-Hsien Huang, Hsien-Wei Chen, Der-Chyang Yeh, Chung-Shi Liu, Shin-Puu Jeng
  • Patent number: 11145614
    Abstract: A method includes placing metal-core solder balls on conductive pads of a first semiconductor device, wherein the metal-core solder balls include a metal core surrounded by a solder material, and forming a device structure, forming the device structure including placing the first semiconductor device on a carrier substrate, encapsulating the first semiconductor device with an encapsulant, wherein the encapsulant covers the metal-core solder balls, performing a planarization process on the encapsulant, wherein the planarization process exposes the metal-core solder balls, and forming a redistribution structure over the encapsulant and the first semiconductor device, wherein the redistribution structure is electrically connected to the metal-core solder balls.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun Yi Wu, Chen-Hua Yu, Chung-Shi Liu
  • Publication number: 20210313671
    Abstract: A package structure including a first redistribution circuit structure, a semiconductor die, first antennas and second antennas is provided. The semiconductor die is located on and electrically connected to the first redistribution circuit structure. The first antennas and the second antennas are located over the first redistribution circuit structure and electrically connected to the semiconductor die through the first redistribution circuit structure. A first group of the first antennas are located at a first position, a first group of the second antennas are located at a second position, and the first position is different from the second position in a stacking direction of the first redistribution circuit structure and the semiconductor die.
    Type: Application
    Filed: June 18, 2021
    Publication date: October 7, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nan-Chin Chuang, Chen-Hua Yu, Chung-Shi Liu, Chao-Wen Shih, Shou-Zen Chang
  • Patent number: 11139249
    Abstract: A packaged semiconductor device including a first die attached to a redistribution structure, a second die attached to the first die, and a molding compound surrounding the first die and the second die and a method of forming the same are disclosed. In an embodiment, a method includes forming first conductive pillars over and electrically coupled to a first redistribution structure; attaching a first die to the first redistribution structure, the first die including second conductive pillars; attaching a second die to the first die adjacent the second conductive pillars; encapsulating the first conductive pillars, the first die, and the second die with an encapsulant; forming a second redistribution structure over the encapsulant, the first conductive pillars, the first die, and the second die; and bonding a third die to the first redistribution structure.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: October 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hung-Yi Kuo, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Tsung-Yuan Yu
  • Publication number: 20210305226
    Abstract: Embodiments of the disclosure provide a package structure and method of forming the same. The package structure includes a first die, a first encapsulant, a first RDL structure, a die stack structure and a second encapsulant. The first encapsulant laterally encapsulates the first die. The first RDL structure is electrically connected to the first die, and disposed on a first side of the first die and the first encapsulant. The die stack structure is electrically connected to the first die and disposed on a second side of the first die opposite to the first side. The second encapsulant is located over the first encapsulant and laterally encapsulating the die stack structure. A sidewall of the first encapsulant is aligned with a sidewall of the second encapsulant.
    Type: Application
    Filed: March 26, 2020
    Publication date: September 30, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang, Wei-Ting Chen
  • Patent number: 11133274
    Abstract: A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: September 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Yen-Chang Hu, Ching-Wen Hsiao, Mirng-Ji Lii, Chung-Shi Liu, Chien Ling Hwang, Chih-Wei Lin, Chen-Shien Chen
  • Patent number: 11133283
    Abstract: Integrated fan-out devices, wafer level packages, and methods of manufacturing the same are described herein. Die-attach pads and leveling film are used to attach a plurality of heterogeneous semiconductor dies to a substrate to align external contacts of the semiconductor dies at a first level. The leveling film may also be used during deposition of an encapsulant to at least partially fill a gap between the semiconductor dies. Once the leveling film is removed, a protection layer is formed over the semiconductor dies and within a recess of the encapsulant left behind by the leveling film during encapsulation. A redistribution layer and external connectors are formed over the protection layer to form the InFO device and an interposer may be attached to the redistribution layer to form the wafer level package.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: September 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun Yi Wu, Chen-Hua Yu, Chung-Shi Liu
  • Publication number: 20210296283
    Abstract: Various embodiments of the present disclosure are directed towards a three-dimensional (3D) trench capacitor, as well as methods for forming the same. In some embodiments, a first substrate overlies a second substrate so a front side of the first substrate faces a front side of the second substrate. A first trench capacitor and a second trench capacitor extend respectively into the front sides of the first and second substrates. A plurality of wires and a plurality of vias are stacked between and electrically coupled to the first and second trench capacitors. A first through substrate via (TSV) extends through the first substrate from a back side of the first substrate, and the wires and the vias electrically couple the first TSV to the first and second trench capacitors. The first and second trench capacitors and the electrical coupling therebetween collectively define the 3D trench capacitor.
    Type: Application
    Filed: March 20, 2020
    Publication date: September 23, 2021
    Inventors: Xin-Hua Huang, Chung-Yi Yu, Yeong-Jyh Lin, Rei-Lin Chu
  • Publication number: 20210288040
    Abstract: A method includes bonding a first device die to a second device die, encapsulating the first device die in a first encapsulant, performing a backside grinding process on the second device die to reveal through-vias in the second device die, and forming first electrical connectors on the second device die to form a package. The package includes the first device die and the second device die. The method further includes encapsulating the first package in a second encapsulant, and forming an interconnect structure overlapping the first package and the second encapsulant. The interconnect structure comprises second electrical connectors.
    Type: Application
    Filed: July 9, 2020
    Publication date: September 16, 2021
    Inventors: Chen-Hua Yu, Hung-Yi Kuo, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Tsung-Yuan Yu, Ming Hung Tseng
  • Patent number: 11121070
    Abstract: A device includes a package. The package includes a plurality of dies, an encapsulant encapsulating the plurality of dies, and a redistribution structure over the plurality of dies and the encapsulant. The device further includes first sockets bonded to a top surface of the redistribution structure and a rigid/flexible substrate bonded to the top surface of the redistribution structure. The rigid/flexible substrate includes a first rigid portion, a second rigid portion, and a flexible portion interposed between the first rigid portion and the second rigid portion. The device further includes second sockets bonded to the first rigid portion of the rigid/flexible substrate and connector modules bonded to the second rigid portion of the rigid/flexible substrate.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Rong Chun, Tin-Hao Kuo, Chi-Hui Lai, Kuo Lung Pan, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20210280524
    Abstract: A package structure includes at least one integrated circuit component, an insulating encapsulation, and a redistribution structure. The at least one integrated circuit component includes a semiconductor substrate, an interconnection structure disposed on the semiconductor substrate, and signal terminals and power terminals located on and electrically connecting to the interconnection structure. The interconnection structure is located between the semiconductor substrate and the signal terminals and between the semiconductor substrate and the power terminals, and where a size of the signal terminals is less than a size of the power terminals. The insulating encapsulation encapsulates the at least one integrated circuit component. The redistribution structure is located on the insulating encapsulation and electrically connected to the at least one integrated circuit component.
    Type: Application
    Filed: May 23, 2021
    Publication date: September 9, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wen Lin, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang, Che-Wei Hsu