Abstract: A process for the polarization transfer between electron spin of Nitrogen Vacancy (NV) centre to nuclear spin of Carbon-13 labelled metabolites (13C-metabolites) in ambient conditions, said process including the steps of (i) providing a mixture including host vehicles which provide a source of NV centres, and 13C-metabolites; (ii) transforming said mixture into a solid glassy state, wherein the spatial orientation of the host and electron spin state of NV centres are randomly distributed within said mixture in a solid state; and (iii) applying a hyperpolarization process to the mixture in a solid state, wherein at the end of polarization transfer process, both electron spin of NV centres and nuclear spin of carbon-13 are strongly polarized in one direction at ambient temperature.

Abstract: A package includes a die. The die includes: a substrate; electrical components at a front side of the substrate; an interconnect structure at the front side of the substrate and electrically coupled to the electrical components, where an uppermost conductive line of the interconnect structure is an aluminum line; and a via extending from the uppermost conductive line to a backside of the substrate. The package further includes: a molding material around the die; a first redistribution structure (RDS) under the die and the molding material; a second RDS over the die and the molding material, where each of the first RDS and the second RDS comprises dielectric layers and conductive features in the dielectric layers, where the via of the die is electrically coupled to the first RDS and the second RDS; and a second die over and electrically coupled to the second RDS.

Abstract: An integrated circuit includes a p-type active zone located in an n-type well, an n-type active zone located in a p-type well, an n-type pick-up region located in the n-type well, and a p-type pick-up region located in the p-type well. The integrated circuit also includes a first power rail and a second power rail extending in a first direction, and a first conductive segment and a second conductive segment extending in a second direction. The first power rail, the p-type active zone, the n-type active zone, and the second power rail are arranged along the second direction separating from each other. The first conductive segment connects the n-type pick-up region with the first power rail, and the second conductive segment connects the p-type pick-up region with the second power rail.

Abstract: A process of assigning a colour grade to a diamond, including the steps of (i) determining the N3 and C-center content of a diamond (110); (ii) comparing the N3 and C-center content of the diamond with a previously acquired data set from a plurality of diamonds each having a colour grading previously assigned thereto, and (iii) assigning a colour grade to the diamond upon a correlation of the N3 and C-center content of said diamond with a grade of said previously acquired data set; wherein said previously acquired data set comprises a correlation between N3 and C center content and optical absorbance in the visible light spectrum for each diamond of said plurality of diamonds.

Abstract: A main board, a hot plug control signal generator, and a control signal generating method thereof are provided. The hot plug control signal generator includes a controller and a latch. The controller provides a control signal. The latch is operated based on an operation power to generate a hot plug control signal. The latch sets the hot plug control signal to a disabled first logic value, and latches the hot plug control signal at the first logic value.

Abstract: A semiconductor device includes a first conductive line extending in a first direction on a front side of a semiconductor wafer, a first power rail extending in the first direction on a back side of the semiconductor wafer, and a first transistor including a first gate structure extending in a second direction perpendicular to the first direction, first and second active regions adjacent to the first gate structure, and a first channel region extending between the first and second active regions through the first gate structure. A first via is positioned between and electrically connects the first active region and the first conductive line, and a second via is positioned between and electrically connects the second active region and the first power rail.

Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

Abstract: An integrated circuit (IC) including a plurality of finfet cells designed with digital circuit design rules to provide smaller finfet cells with decreased cell heights, and analog circuit cell structures including first finfet cells of the plurality of finfet cells and including at least one cut metal layer. The smaller finfet cells with decreased cell heights provide a first shorter metal track in one direction and the at least one cut metal layer provides a second shorter metal track in another direction to increase maximum electromigration currents in the integrated circuit.

Abstract: A printhead in a digital printing includes an array of light sources for exposing a photosensitive medium moving past the printhead. Artifacts are reduced in a high-speed print mode by defining first and a second power level control values that differ by at least 20%. The light sources used to print odd-numbered image pixels are activated responsive to the first power level control value and the light sources used to print even-numbered image pixels are activated responsive to the second power level control value.

Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

Abstract: A method includes identifying at least a first mask or a second mask, fabricating, by the first mask, a first conductive line, fabricating, by the second mask, a second conductive line, and fabricating, by the first mask, a third conductive line if a dimension of the first conductive line is larger than a corresponding dimension of the second conductive line, or fabricating, by the second mask, the third conductive line if the dimension of the first conductive line is less than the corresponding dimension of the second conductive line A first circuit element is coupled to a second circuit element by at least the third conductive line, and the first circuit element is separated from the second circuit element by a predetermined distance.

Abstract: The present disclosure describes structure with a substrate, a first well region, a second well region, and a third well region. The first well region is in the substrate. The second well region is in the first well region and includes a first source/drain (S/D) region. The third well region is in the substrate and adjacent to the first well region. The third well region includes a second S/D region, where a spacing between the first and second S/D regions is less than about 3 ?m.

Abstract: An integrated circuit includes a first power rail; a p-type active zone located in an n-type well; an n-type pick-up region located at least in part in the n-type well and forming a first guard-ring around the p-type active zone; a first conductive segment connecting the n-type pick-up region to the first power rail; an n-type active zone located in a p-type well; a p-type pick-up region located at least in part in the p-type well and forming a second guard-ring around the n-type active zone; a second power rail; and a second conductive segment connecting the p-type pick-up region to the second power rail. An n-type dopant concentration of the n-type pick-up region is higher than an n-type dopant concentration of the n-type well, and a p-type dopant concentration of the p-type pick-up region is higher than a p-type dopant concentration of the p-type well.

Abstract: A semiconductor device includes in a transistor layer, components of corresponding transistors (transistor components); in corresponding layers below the transistor layer (sub-TR layers), various non-dummy structures (non-dummy sub-TR structures) coupled to the transistor components and which are included because the semiconductor device has a buried power rail (BPR) architecture; and in corresponding layers over the transistor layer (supra-TR layers), various dummy structures (dummy supra-TR structures) which are included as artifacts resulting from the semiconductor device being based on a dual-architecture-compatible design which is substantially equally suitable either to adaptation into a non-BPR architecture or adaptation into the BPR architecture; and the semiconductor device being an inductor.

Abstract: A semiconductor device includes an active area structure extending in a first direction; gate structures over the active area structure and extending in a second direction, the gate structures including a first gate structure and a second gate structure; contact-source/drain (CSD) conductors over the active area structure, interleaved with corresponding ones of the gate structures, and extending in the second direction; via-on-gate (VG) structures, the VG structures including a first VG structure over the first gate structure and a second VG structure over the second gate structure; and first conductive segments in a first layer of metallization (M_1st layer) over the active area structure and extending in the first direction, the first conductive segments including a first gate-signal-carrying (GSC) conductor which overlaps the active area structure, extends over the first and second VG structures, and is electrically coupled in common with each of the first and second gate structures.

Abstract: A semiconductor device includes a substrate. A first nanosheet structure and a second nanosheet structure are disposed on the substrate. Each of the first and second nanosheet structures have at least one nanosheet forming source/drain regions and a gate structure including a conductive gate contact. A first oxide structure is disposed on the substrate between the first and second nanosheet structures. A conductive terminal is disposed in or on the first oxide structure. The conductive terminal, the first oxide structure and the gate structure of the first nanosheet structure define a capacitor.

Abstract: A process of forming a non-optically detectable authentication marking (210,320, 410,535) in a diamond (200,300). Authentication marking (210,320,410,535) is formed adjacent the outer surface of an article formed from a diamond material having intrinsic optical centers. Method includes the step of applying an image of predesigned authentication marking (210,320,410,535) to a region (201,310,530) of a diamond (200,300) at or adjacent the surface of the diamond (200,300) by way of a direct laser writing; wherein the fluorescence background of the diamond material from intrinsic optical center is suppressed by authentication marking (210,320, 410, 535) under fluorescent imaging, such that the non-optically detectable identifiable authentication marking (210,320,410,535) is viewable against the fluorescence background at the region (201,310,530) of the diamond (200,300) where the authentication marking (210,320,410,535) is applied.

Abstract: The present disclosure describes structure with a substrate, a first well region, a second well region, and a third well region. The first well region is in the substrate. The second well region is in the first well region and includes a first source/drain (S/D) region. The third well region is in the substrate and adjacent to the first well region. The third well region includes a second S/D region, where a spacing between the first and second S/D regions is less than about 3 ?m.

Abstract: An analog standard cell is provided. An analog standard cell according to the present disclosure includes a first active region and a second active region extending along a first direction, and a plurality of conductive lines in a first metal layer over the first active region and the second active region. The plurality of conductive lines includes a first conductive line and a second conductive line disposed directly over the first active region, a third conductive line and a fourth conductive line disposed directly over the second active region, a middle conductive line disposed between the second conductive line and the third conductive line, a first power line spaced apart from the middle conductive line by the first conductive line and the second conductive line, and a second power line spaced apart from the middle conductive line by the third conductive line and the fourth conductive line.

Abstract: An integrated circuit (IC) device includes a substrate having opposite first and second sides, and a circuit over the first side of the substrate and including a first transistor and a second transistor. A first terminal of the first transistor is electrically coupled to a second terminal of the second transistor both over the first side of the substrate and under the second side of the substrate.