Patents by Inventor Chung-Hung Liu

Chung-Hung Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240136317
    Abstract: According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Inventors: Wei-Hung Lin, Hsiu-Jen Lin, Ming-Da Cheng, Yu-Min Liang, Chen-Shien Chen, Chung-Shi Liu
  • Patent number: 11966107
    Abstract: An anti-peep display device includes a display module and an anti-peep module disposed on the display module. The anti-peep module includes the following features. The first light incident surface faces the display surface, the second and third light incident surfaces are located on opposite sides of the first light incident surface, the first condensing portion is disposed corresponding to the second light incident surface and the first light source, the second condensing portion is disposed corresponding to the third light incident surface and the second light source, the first and second condensing portions convert beams of the first and second light sources into anti-peep beams with a beam angle less than 10 degrees, and the optical microstructures reflect the anti-peep beams and exit the anti-peep beams from the light guide plate. The present invention also provides an anti-peep method applicable to the anti-peep display device.
    Type: Grant
    Filed: June 14, 2023
    Date of Patent: April 23, 2024
    Assignee: CHAMP VISION DISPLAY INC.
    Inventors: Chung-Hao Wu, Hsin-Hung Lee, Chin-Ku Liu, Chun-Chien Liao, Wei-Jhe Chien
  • Patent number: 11955460
    Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Da Tsai, Meng-Tse Chen, Sheng-Feng Weng, Sheng-Hsiang Chiu, Wei-Hung Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
  • Publication number: 20240105775
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first source/drain structure and a second source/drain structure over and in a substrate. The method includes forming a first gate stack, a second gate stack, a third gate stack, and a fourth gate stack over the substrate. Each of the first gate stack or the second gate stack is wider than each of the third gate stack or the fourth gate stack. The method includes forming a first contact structure and a second contact structure over the first source/drain structure and the second source/drain structure respectively. A first average width of the first contact structure is substantially equal to a second average width of the second contact structure.
    Type: Application
    Filed: February 9, 2023
    Publication date: March 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yu CHIANG, Hsiao-Han LIU, Yuan-Hung TSENG, Chih-Yung LIN
  • Patent number: 11935871
    Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Cheng-Chieh Hsieh, Tsung-Hsien Chiang, Hui-Chun Chiang, Tzu-Sung Huang, Ming-Hung Tseng, Kris Lipu Chuang, Chung-Ming Weng, Tsung-Yuan Yu, Tzuan-Horng Liu
  • Patent number: 11933309
    Abstract: A method for controlling a fan in a fan start-up stage including a first time period and a second time period comprises the following steps of: during the first time period, continuously providing a first driving signal to drive the fan; and during the second time period, continuously providing a second driving signal to drive the fan; wherein, the signal value of the first driving signal gradually decreases until being equal to the signal value of the second driving signal. Wherein the signal value of the first driving signal non-linearly decreases, the signal value of the second driving signal is an unchanged value. Wherein, the first time period and the second time period are adjusted for a different fan but the sum of the first time period and the second time period is always the same. A fan is also disclosed.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: March 19, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yi-Fan Lin, Chung-Hung Tang, Cheng-Chieh Liu, Chun-Lung Chiu
  • Patent number: 11935804
    Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Ming Hung Tseng, Yen-Liang Lin, Hao-Yi Tsai, Chi-Ming Tsai, Chung-Shi Liu, Chih-Wei Lin, Ming-Che Ho
  • Patent number: 11410681
    Abstract: In one or more embodiments, one or more system, methods, and/or processes may determine, based at least on the user responses from users that listen to audio files, first portions of the audio files that include at least one audio glitch and second portions of the audio files that do not include the at least one audio glitch; may determine values of a filter, of a convolution neural network (CNN), based at least on the first portions and the second portions of the audio files; may provide audio produced by an information handling system (IHS) to the CNN; may determine, based at least on data from convolving the audio produced by the IHS with the filter and output data from the CNN, if the IHS has produced an audio glitch; and may provide information indicating whether or not the IHS has produced the audio glitch.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: August 9, 2022
    Assignee: Dell Products L.P.
    Inventor: Chung-Hung Liu
  • Patent number: 11348586
    Abstract: Systems and methods are provided that that may be implemented to extend functionality of a voice assistant and/or telecommunications software to a remote location via an endpoint device.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: May 31, 2022
    Assignee: Dell Products L.P.
    Inventors: Kang Ou-Yang, Michael Wu, Chung-Hung Liu, Chen Yang Chen, Hsuan-Yin Tsai
  • Publication number: 20210272583
    Abstract: In one or more embodiments, one or more system, methods, and/or processes may determine, based at least on the user responses from users that listen to audio files, first portions of the audio files that include at least one audio glitch and second portions of the audio files that do not include the at least one audio glitch; may determine values of a filter, of a convolution neural network (CNN), based at least on the first portions and the second portions of the audio files; may provide audio produced by an information handling system (IHS) to the CNN; may determine, based at least on data from convolving the audio produced by the IHS with the filter and output data from the CNN, if the IHS has produced an audio glitch; and may provide information indicating whether or not the IHS has produced the audio glitch.
    Type: Application
    Filed: March 2, 2020
    Publication date: September 2, 2021
    Inventor: Chung-Hung Liu
  • Publication number: 20190392838
    Abstract: Systems and methods are provided that that may be implemented to extend functionality of a voice assistant and/or telecommunications software to a remote location via an endpoint device.
    Type: Application
    Filed: June 21, 2018
    Publication date: December 26, 2019
    Inventors: Kang Ou-Yang, Michael Wu, Chung-Hung Liu, Chen Yang Chen, Hsuan-Yin Tsai