Patents by Inventor Chung-Hwan Shin

Chung-Hwan Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250072096
    Abstract: A method of fabricating a semiconductor device includes: forming an active pattern on a substrate, forming a source/drain pattern on the active pattern, forming a contact hole on the source/drain pattern, forming a contact barrier layer, which has an upper surface of a first height based on a bottom surface of the contact hole, in the contact hole, forming a passivation layer on the contact barrier layer in the contact hole, forming a mask layer on the passivation layer in the contact hole, removing an upper portion of the contact barrier layer so that an upper surface of the contact barrier layer has a second height lower than the first height, removing the passivation layer and the mask layer, and forming a contact filling layer, which covers the upper surface of the contact barrier layer and fills the contact hole, in the contact hole.
    Type: Application
    Filed: March 15, 2024
    Publication date: February 27, 2025
    Inventors: Gi Woong SHIM, Seong Heum CHOI, Do Sun LEE, Hyo Seok CHOI, Rak Hwan KIM, Chung Hwan SHIN
  • Patent number: 12165916
    Abstract: A semiconductor device includes a first interlayer insulating film; a conductive connection structure provided in the first interlayer insulating film; a second interlayer insulating film provided on the first interlayer insulating film; a wiring structure provided in the second interlayer insulating film and connected to the conductive connection structure; and an insertion liner interposed between an upper surface of the conductive connection structure and the wiring structure, the insertion liner including carbon.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: December 10, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won Keun Chung, Joon Gon Lee, Rak Hwan Kim, Chung Hwan Shin, Do Sun Lee, Nam Gyu Cho
  • Publication number: 20240405090
    Abstract: A semiconductor device is provided. The semiconductor device includes: a semiconductor device including: an active pattern extending in a first direction; a gate structure including a gate electrode extending in a second direction and a gate spacer on the active pattern, wherein the gate electrode and the gate spacer are spaced apart from each other in the first direction; a source/drain pattern on the active pattern; a contact barrier layer on the source/drain pattern; and a contact filling layer on the contact barrier layer. An uppermost point of the contact barrier layer is between an upper surface of the contact filling layer and a lower surface of the contact filling layer, and outer walls of the contact barrier layer and outer walls of the contact filling layer extend along a common plane.
    Type: Application
    Filed: December 20, 2023
    Publication date: December 5, 2024
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seong Heum CHOI, Jeong Hoon SEO, Rak Hwan KIM, Chung Hwan SHIN, Do Sun LEE
  • Publication number: 20240332381
    Abstract: A semiconductor device may include an active pattern extending in a first direction, a gate structure which is placed on the active pattern to be spaced apart from each other in the first direction, and includes a gate electrode and a gate spacer, the gate electrode extending in a second direction intersecting the first direction, a gate contact on the gate structure, a source/drain pattern on the active pattern, a source/drain contact on the source/drain pattern, and a via plug on the source/drain contact. An upper surface of the gate contact and a second upper surface of the via plug may be placed on the same plane. A lower surface of the gate contact and a lower surface of the via plug may be different in height, on the basis of an upper surface of the active pattern.
    Type: Application
    Filed: October 20, 2023
    Publication date: October 3, 2024
    Inventors: Ji Won KANG, Chung Hwan SHIN, Seong Heum CHOI, Rak Hwan KIM
  • Patent number: 11923426
    Abstract: A semiconductor device capable of improving a device performance and a reliability is provided. The semiconductor device comprising a gate structure including a gate electrode on a substrate, a source/drain pattern on a side face of the gate electrode, on the substrate and, a source/drain contact connected to the source/drain pattern, on the source/drain pattern, a gate contact connected to the gate electrode, on the gate electrode, and a wiring structure connected to the source/drain contact and the gate contact, on the source/drain contact and the gate contact, wherein the wiring structure includes a first via plug, a second via plug, and a wiring line connected to the first via plug and the second via plug, the first via plug has a single conductive film structure, and the second via plug includes a lower via filling film, and an upper via filling film on the lower via filling film.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: March 5, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji Won Kang, Tae-Yeol Kim, Jeong Ik Kim, Rak Hwan Kim, Jun Ki Park, Chung Hwan Shin
  • Publication number: 20240014250
    Abstract: A semiconductor device is provided including a resistor structure, the semiconductor device including a substrate having an upper surface perpendicular to a first direction; a resistor structure including a first insulating layer on the substrate, a resistor layer on the first insulating layer, and a second insulating layer on the resistor layer; and a resistor contact penetrating the second insulating layer and the resistor layer. The tilt angle of a side wall of the resistor contact with respect to the first direction varies according to a height from the substrate. The semiconductor device has a low contact resistance and a narrow variation of contact resistance.
    Type: Application
    Filed: September 21, 2023
    Publication date: January 11, 2024
    Inventors: Tae-yeol KIM, Hyon-wook RA, Seo-bum LEE, Jun-soo KIM, Chung-hwan SHIN
  • Patent number: 11804516
    Abstract: A semiconductor device is provided including a resistor structure, the semiconductor device including a substrate having an upper surface perpendicular to a first direction; a resistor structure including a first insulating layer on the substrate, a resistor layer on the first insulating layer, and a second insulating layer on the resistor layer; and a resistor contact penetrating the second insulating layer and the resistor layer. The tilt angle of a side wall of the resistor contact with respect to the first direction varies according to a height from the substrate. The semiconductor device has a low contact resistance and a narrow variation of contact resistance.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: October 31, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-yeol Kim, Hyon-wook Ra, Seo-bum Lee, Jun-soo Kim, Chung-hwan Shin
  • Publication number: 20220319916
    Abstract: A semiconductor device includes a first interlayer insulating film; a conductive connection structure provided in the first interlayer insulating film; a second interlayer insulating film provided on the first interlayer insulating film; a wiring structure provided in the second interlayer insulating film and connected to the conductive connection structure; and an insertion liner interposed between an upper surface of the conductive connection structure and the wiring structure, the insertion liner including carbon.
    Type: Application
    Filed: June 13, 2022
    Publication date: October 6, 2022
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won Keun CHUNG, Joon Gon LEE, Rak Hwan KIM, Chung Hwan SHIN, Do Sun LEE, Nam Gyu CHO
  • Patent number: 11367651
    Abstract: A semiconductor device includes a first interlayer insulating film; a conductive connection structure provided in the first interlayer insulating film; a second interlayer insulating film provided on the first interlayer insulating film; a wiring structure provided in the second interlayer insulating film and connected to the conductive connection structure; and an insertion liner interposed between an upper surface of the conductive connection structure and the wiring structure, the insertion liner including carbon.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: June 21, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won Keun Chung, Joon Gon Lee, Rak Hwan Kim, Chung Hwan Shin, Do Sun Lee, Nam Gyu Cho
  • Publication number: 20220130970
    Abstract: A semiconductor device capable of improving a device performance and a reliability is provided. The semiconductor device comprising a gate structure including a gate electrode on a substrate, a source/drain pattern on a side face of the gate electrode, on the substrate and, a source/drain contact connected to the source/drain pattern, on the source/drain pattern, a gate contact connected to the gate electrode, on the gate electrode, and a wiring structure connected to the source/drain contact and the gate contact, on the source/drain contact and the gate contact, wherein the wiring structure includes a first via plug, a second via plug, and a wiring line connected to the first via plug and the second via plug, the first via plug has a single conductive film structure, and the second via plug includes a lower via filling film, and an upper via filling film on the lower via filling film.
    Type: Application
    Filed: July 6, 2021
    Publication date: April 28, 2022
    Inventors: Ji Won KANG, Tae-Yeol KIM, Jeong Ik KIM, Rak Hwan KIM, Jun Ki PARK, Chung Hwan SHIN
  • Publication number: 20210098563
    Abstract: A semiconductor device is provided including a resistor structure, the semiconductor device including a substrate having an upper surface perpendicular to a first direction; a resistor structure including a first insulating layer on the substrate, a resistor layer on the first insulating layer, and a second insulating layer on the resistor layer; and a resistor contact penetrating the second insulating layer and the resistor layer. The tilt angle of a side wall of the resistor contact with respect to the first direction varies according to a height from the substrate. The semiconductor device has a low contact resistance and a narrow variation of contact resistance.
    Type: Application
    Filed: December 10, 2020
    Publication date: April 1, 2021
    Inventors: Tae-yeol KIM, Hyon-wook RA, Seo-bum LEE, Jun-soo KIM, Chung-hwan SHIN
  • Publication number: 20210020500
    Abstract: A semiconductor device includes a first interlayer insulating film; a conductive connection structure provided in the first interlayer insulating film; a second interlayer insulating film provided on the first interlayer insulating film; a wiring structure provided in the second interlayer insulating film and connected to the conductive connection structure; and an insertion liner interposed between an upper surface of the conductive connection structure and the wiring structure, the insertion liner including carbon.
    Type: Application
    Filed: June 16, 2020
    Publication date: January 21, 2021
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won Keun Chung, Joon Gon Lee, Rak Hwan Kim, Chung Hwan Shin, Do Sun Lee, Nam Gyu Cho
  • Patent number: 10886361
    Abstract: A semiconductor device is provided including a resistor structure, the semiconductor device including a substrate having an upper surface perpendicular to a first direction; a resistor structure including a first insulating layer on the substrate, a resistor layer on the first insulating layer, and a second insulating layer on the resistor layer; and a resistor contact penetrating the second insulating layer and the resistor layer. The tilt angle of a side wall of the resistor contact with respect to the first direction varies according to a height from the substrate. The semiconductor device has a low contact resistance and a narrow variation of contact resistance.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: January 5, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-yeol Kim, Hyon-wook Ra, Seo-bum Lee, Jun-soo Kim, Chung-hwan Shin
  • Patent number: 10847464
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device including an insulating structure having an opening; a conductive pattern disposed in the opening; a barrier structure covering a bottom surface of the conductive pattern, the barrier structure extending between the conductive pattern and side walls of the opening; and a nucleation structure disposed between the conductive pattern and the barrier structure. The nucleation structure includes a first nucleation layer that contacts the barrier structure, and a second nucleation layer that contacts the conductive pattern, and a top end portion of the second nucleation layer is higher than a top end portion of the first nucleation layer.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: November 24, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae Yeol Kim, Ji Won Kang, Chung Hwan Shin, Jin Il Lee, Sang Jin Hyun
  • Patent number: 10840374
    Abstract: A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: November 17, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chung-Hwan Shin, Sang-Bom Kang, Dae-Yong Kim, Jeong-Ik Kim, Chul-Sung Kim, Je-Hyung Ryu, Sang-Woo Lee, Hyo-Seok Choi
  • Publication number: 20200152577
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device including an insulating structure having an opening; a conductive pattern disposed in the opening; a barrier structure covering a bottom surface of the conductive pattern, the barrier structure extending between the conductive pattern and side walls of the opening; and a nucleation structure disposed between the conductive pattern and the barrier structure. The nucleation structure includes a first nucleation layer that contacts the barrier structure, and a second nucleation layer that contacts the conductive pattern, and a top end portion of the second nucleation layer is higher than a top end portion of the first nucleation layer.
    Type: Application
    Filed: January 9, 2020
    Publication date: May 14, 2020
    Inventors: TAE YEOL KIM, JI WON KANG, CHUNG HWAN SHIN, JIN IL LEE, SANG JIN HYUN
  • Patent number: 10580736
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device including an insulating structure having an opening; a conductive pattern disposed in the opening; a barrier structure covering a bottom surface of the conductive pattern, the barrier structure extending between the conductive pattern and side walls of the opening; and a nucleation structure disposed between the conductive pattern and the barrier structure. The nucleation structure includes a first nucleation layer that contacts the barrier structure, and a second nucleation layer that contacts the conductive pattern, and a top end portion of the second nucleation layer is higher than a top end portion of the first nucleation layer.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: March 3, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae Yeol Kim, Ji Won Kang, Chung Hwan Shin, Jin Il Lee, Sang Jin Hyun
  • Publication number: 20190295958
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device including an insulating structure having an opening; a conductive pattern disposed in the opening; a barrier structure covering a bottom surface of the conductive pattern, the barrier structure extending between the conductive pattern and side walls of the opening; and a nucleation structure disposed between the conductive pattern and the barrier structure. The nucleation structure includes a first nucleation layer that contacts the barrier structure, and a second nucleation layer that contacts the conductive pattern, and a top end portion of the second nucleation layer is higher than a top end portion of the first nucleation layer.
    Type: Application
    Filed: June 14, 2019
    Publication date: September 26, 2019
    Inventors: TAE YEOL KIM, JI WON KANG, CHUNG HWAN SHIN, JIN IL LEE, SANG JIN HYUN
  • Patent number: 10366955
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device including an insulating structure having an opening; a conductive pattern disposed in the opening; a barrier structure covering a bottom surface of the conductive pattern, the barrier structure extending between the conductive pattern and side walls of the opening; and a nucleation structure disposed between the conductive pattern and the barrier structure. The nucleation structure includes a first nucleation layer that contacts the barrier structure, and a second nucleation layer that contacts the conductive pattern, and a top end portion of the second nucleation layer is higher than a top end portion of the first nucleation layer.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: July 30, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae Yeol Kim, Ji Won Kang, Chung Hwan Shin, Jin Il Lee, Sang Jin Hyun
  • Publication number: 20180374915
    Abstract: A semiconductor device is provided including a resistor structure, the semiconductor device including a substrate having an upper surface perpendicular to a first direction; a resistor structure including a first insulating layer on the substrate, a resistor layer on the first insulating layer, and a second insulating layer on the resistor layer; and a resistor contact penetrating the second insulating layer and the resistor layer. The tilt angle of a side wall of the resistor contact with respect to the first direction varies according to a height from the substrate. The semiconductor device has a low contact resistance and a narrow variation of contact resistance.
    Type: Application
    Filed: January 5, 2018
    Publication date: December 27, 2018
    Inventors: Tae-yeol KIM, Hyon-wook RA, Seo-bum LEE, Jun-soo KIM, Chung-hwan SHIN