Patents by Inventor CHUNG-HYUN LEE

CHUNG-HYUN LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240236693
    Abstract: Disclosed are a semi-distributed spectrum sensing method in cognitive IoT networks, and an apparatus thereof. The semi-distributed spectrum sensing method in cognitive IoT networks includes: (a) grouping, based on local information of pre-shared secondary terminals, each secondary terminal into each local cluster; (b) generating overlapping point information by calculating an overlapping range between directional antenna beams of the respective secondary terminals in the each local cluster, and determining a beam determination binary indicator of the each secondary terminal by using the overlapping point information; and (c) calculating and adjusting the overlapping range between the respective local clusters.
    Type: Application
    Filed: January 10, 2024
    Publication date: July 11, 2024
    Inventors: Sung Rae CHO, Chung Hyun LEE, Dong Hyun LEE, Jun Suk OH
  • Patent number: 11656186
    Abstract: Disclosed is a method for analyzing a shape of a wafer. The method includes measuring external shapes of a plurality of wafers, detecting a first point having a maximum curvature in an edge region of each wafer from measured values acquired in the measuring the external shapes of the wafers, detecting a second point spaced apart from the first point in a direction towards an apex of a corresponding one of the wafers, measuring a first angle formed between a first line configured to connect the first point and the second point and a front side of the corresponding one of the wafers, forming a thin film layer on a surface of each wafer, measuring a thickness profile of the thin film layer, and confirming a wafer in which a maximum value of the thickness profile of the thin film layer is the smallest among the wafers.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: May 23, 2023
    Assignee: SK SILTRON CO., LTD.
    Inventor: Chung Hyun Lee
  • Publication number: 20220279810
    Abstract: A confectionery product comprising of a layer of gummy confectionery, made up of one or more sections, which coat a non-edible object or container. This container is purposed to house a children's toy and support the layer of confectionery. Methods of preparing the confectionery-coated object also are provided.
    Type: Application
    Filed: August 7, 2020
    Publication date: September 8, 2022
    Inventors: Chung Hyun Lee, David Johnston Smith, Diwata Katrina Dinglasa Santillan, Ethan Luke Harrold, Ethan Hutchinson
  • Publication number: 20220018788
    Abstract: Disclosed is a method for analyzing a shape of a wafer. The method includes measuring external shapes of a plurality of wafers, detecting a first point having a maximum curvature in an edge region of each wafer from measured values acquired in the measuring the external shapes of the wafers, detecting a second point spaced apart from the first point in a direction towards an apex of a corresponding one of the wafers, measuring a first angle formed between a first line configured to connect the first point and the second point and a front side of the corresponding one of the wafers, forming a thin film layer on a surface of each wafer, measuring a thickness profile of the thin film layer, and confirming a wafer in which a maximum value of the thickness profile of the thin film layer is the smallest among the wafers.
    Type: Application
    Filed: October 13, 2020
    Publication date: January 20, 2022
    Inventor: Chung Hyun LEE
  • Patent number: 9905656
    Abstract: Provided is a semiconductor substrate including a seed layer disposed on a substrate, a buffer layer disposed on the seed layer, a plurality of nitride semiconductor layers disposed on the buffer layer, and at least one stress control layer between the plurality of nitride semiconductor layers. The buffer layer includes a plurality of step regions and at least one heterogeneous region. The plurality of step regions includes the same nitride semiconductor material. The heterogeneous region includes a different nitride semiconductor material from the step regions.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: February 27, 2018
    Assignee: SK Siltron Co., Ltd.
    Inventors: Kye-Jin Lee, Ho-Jun Lee, Young-Jae Choi, Jung-Hyun Eum, Chung-Hyun Lee
  • Publication number: 20170141195
    Abstract: Provided is a semiconductor substrate including a seed layer disposed on a substrate, a buffer layer disposed on the seed layer, a plurality of nitride semiconductor layers disposed on the buffer layer, and at least one stress control layer between the plurality of nitride semiconductor layers. The buffer layer includes a plurality of step regions and at least one heterogeneous region. The plurality of step regions includes the same nitride semiconductor material. The heterogeneous region includes a different nitride semiconductor material from the step regions.
    Type: Application
    Filed: January 3, 2017
    Publication date: May 18, 2017
    Inventors: Kye-Jin LEE, Ho-Jun LEE, Young-Jae CHOI, Jung-Hyun EUM, Chung-Hyun LEE
  • Patent number: 9583575
    Abstract: Provided is a semiconductor substrate including a seed layer disposed on a substrate, a buffer layer disposed on the seed layer, a plurality of nitride semiconductor layers disposed on the buffer layer, and at least one stress control layer between the plurality of nitride semiconductor layers. The buffer layer includes a plurality of step regions and at least one heterogeneous region. The plurality of step regions includes the same nitride semiconductor material. The heterogeneous region includes a different nitride semiconductor material from the step regions.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: February 28, 2017
    Assignee: LG SILTRON INC.
    Inventors: Kye-Jin Lee, Ho-Jun Lee, Young-Jae Choi, Jung-Hyun Eum, Chung-Hyun Lee
  • Publication number: 20150357418
    Abstract: Provided is a semiconductor substrate including a seed layer disposed on a substrate, a buffer layer disposed on the seed layer, a plurality of nitride semiconductor layers disposed on the buffer layer, and at least one stress control layer between the plurality of nitride semiconductor layers. The buffer layer includes a plurality of step regions and at least one heterogeneous region. The plurality of step regions includes the same nitride semiconductor material. The heterogeneous region includes a different nitride semiconductor material from the step regions.
    Type: Application
    Filed: January 3, 2014
    Publication date: December 10, 2015
    Applicant: LG SILTRON INC.
    Inventors: Kye-Jin LEE, Ho-Jun LEE, Young-Jae CHOI, Jung-Hyun EUM, Chung-Hyun LEE
  • Patent number: 8879320
    Abstract: A method of programming a multi-level cells (MLC) commonly coupled to a word line in a non-volatile memory device includes shadow-programming first MLC to a first shadow state, shadow-programming second MLC to a second shadow state less than the first shadow state, and then main-programming the first MLC from the first shadow state to a first final state and main-programming the second MLC from the second shadow state to the second final state less than the first final state.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: November 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chung-Hyun Lee, Ki-Hwan Choi
  • Publication number: 20130135929
    Abstract: A method of programming a multi-level cells (MLC) commonly coupled to a word line in a non-volatile memory device includes shadow-programming first MLC to a first shadow state, shadow-programming second MLC to a second shadow state less than the first shadow state, and then main-programming the first MLC from the first shadow state to a first final state and main-programming the second MLC from the second shadow state to the second final state less than the first final state.
    Type: Application
    Filed: September 12, 2012
    Publication date: May 30, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: CHUNG-HYUN LEE, KI-HWAN CHOI
  • Patent number: D1009402
    Type: Grant
    Filed: April 12, 2023
    Date of Patent: January 2, 2024
    Assignee: Zuru (Singapore) Pte. Ltd.
    Inventors: Mathew Peter Mowbray, Chung Hyun Lee, David Johnston Smith, Diwata Katrina Dinglasa Santillan, Ethan Luke Harrold, Ethan Hutchinson
  • Patent number: D1012421
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: January 30, 2024
    Assignee: Zuru (Singapore) Pte. Ltd.
    Inventors: Mathew Peter Mowbray, Chung Hyun Lee, David Johnston Smith, Diwata Katrina Dinglasa Santillan, Ethan Luke Harrold, Ethan Hutchinson
  • Patent number: D1023504
    Type: Grant
    Filed: September 28, 2023
    Date of Patent: April 23, 2024
    Assignee: Zuru (Singapore) Pte. Ltd.
    Inventors: Mathew Peter Mowbray, Chung Hyun Lee, David Johnston Smith, Diwata Katrina Dinglasa Santillan, Ethan Luke Harrold, Ethan Hutchinson
  • Patent number: D1050667
    Type: Grant
    Filed: January 12, 2024
    Date of Patent: November 12, 2024
    Assignee: ZURU (SINGAPORE) PTE. LTD.
    Inventors: Mathew Peter Mowbray, Chung Hyun Lee, David Johnston Smith, Diwata Katrina Dinglasa Santillan, Ethan Luke Harrold, Ethan Hutchinson
  • Patent number: D1052222
    Type: Grant
    Filed: January 12, 2024
    Date of Patent: November 26, 2024
    Assignee: ZURU (SINGAPORE) PTE. LTD.
    Inventors: Mathew Peter Mowbray, Chung Hyun Lee, David Johnston Smith, Diwata Katrina Dinglasa Santillan, Ethan Luke Harrold, Ethan Hutchinson
  • Patent number: D1056398
    Type: Grant
    Filed: March 29, 2024
    Date of Patent: January 7, 2025
    Assignee: ZURU (SINGAPORE) PTE. LTD.
    Inventors: Mathew Peter Mowbray, Chung Hyun Lee, David Johnston Smith, Diwata Katrina Dinglasa Santillan, Ethan Luke Harrold, Ethan Hutchinson