Patents by Inventor Chung-I Chen

Chung-I Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7631577
    Abstract: A bicycle treadle device comprises a treadle having an axial hole at a center portion thereof; at least one control block being installed at the treadle near the locking sheet; the control block being installed to the treadle; the control block being formed by a main ring; a first protrusion and a second protrusion being protruded from the main ring which has different sizes. By rotating the control block, it can be adjusted so that one of the main ring, the first protrusion and the second protrusion to resist against the front locking sheet of the locking sheet to adjust the expansion of the front locking sheet. Furthermore an adjusting unit is used to change the tightness of the elastic unit of the locking sheet.
    Type: Grant
    Filed: February 23, 2007
    Date of Patent: December 15, 2009
    Inventor: Chung-I Chen
  • Publication number: 20090241725
    Abstract: A modularized pedal assembly includes an axial portion and a pedaling portion. The axial portion includes a spindle and a bush. The spindle is engaged to the bush. Each of two ends of the bush is formed with at least one protruding seat. Each pedaling portion has at least one combining space. The combining space is at one side of the pedaling portion and is extended inwards so that the pedaling portion is formed as an upper layer and a lower layer; and the pedaling portion is engaged to the protruding seats at two sides of the axial portion so that the pedaling portion is detachable from the axial portion. The pedal and crank are not detached frequently so as to retain the stability of the structure. The pedaling portion is replaceable and changeable to match the requirement of users and thus it is economic.
    Type: Application
    Filed: March 27, 2008
    Publication date: October 1, 2009
    Inventor: Chung-I CHEN
  • Publication number: 20090235778
    Abstract: A positioning shoe retainer assembly of a bicycle comprises a shoe retainer and a pedal. The shoe retainer has a retaining portion which is installed with at least one engaging hole for retaining. An arc portion is extending from the retaining portion; an inner side of the arc portion being formed with a receiving portion. The arc portion is extending with a combining portion. The combining seat is installed with a combining seat. At least one combining unit is extending from the combining seat 131. The pedal serves to assembled with a bicycle by connecting to a shaft of a bicycle. A surface of the pedal adjacent to the shaft is an inner lateral surface; and a surface of the pedal opposite to the inner lateral surface being an outer lateral surface. An upper surface of the pedal is formed as a treaded surface for being treaded by users.
    Type: Application
    Filed: March 21, 2008
    Publication date: September 24, 2009
    Inventor: Chung-I Chen
  • Patent number: 7526982
    Abstract: A bicycle toe positioning device comprises a treadle having a main body which is formed with an axial hole, an axial rod and a bearing set. The treadle is further formed with a first clamping portion and a second clamping portion. A tightening unit has a first positioning end and a second positioning end. In assembly, the first clamping portion is buckled to a rib and a pair of wings of the first positioning end. The second clamping portion is secured to the second positioning end so that the treadle is secured to the toe positioning unit. The first clamping portion has a buckling block which is fixed to the treadle by using an pivotal rod. A spring is retained in the first clamping portion and an adjust unit serves to adjust the tightness of the buckling block.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: May 5, 2009
    Inventor: Chung-I Chen
  • Patent number: 7509889
    Abstract: A bicycle pedal assembly includes a pedal body having a sleeve tube and front and rear protruding portions. A front clamping member is mounted rotatably on the front protruding portion, and is biased by a front biasing member to rotate toward the sleeve tube. A locking member is connected to the front protruding portion, and is operable to abut against the front clamping member so as to lock the latter against rotational movement. A rear clamping member is mounted rotatably on the rear protruding portion, and is biased by a rear biasing member to rotate toward the sleeve tube. An adjusting member is connected to the rear clamping member, and is operable to adjust the biasing force of the rear biasing member.
    Type: Grant
    Filed: November 29, 2006
    Date of Patent: March 31, 2009
    Inventor: Chung-I Chen
  • Patent number: 7498653
    Abstract: A semiconductor structure for isolating a first circuit and a second circuit of various operating voltages includes a first isolation ring surrounding the first and second circuits on a semiconductor substrate. A buried layer continuously extending underneath the first and second circuits is formed on the semiconductor substrate, wherein the buried layer interfaces with the first isolation ring for isolating the first and second circuits from a backside bias of the semiconductor substrate. An ion enhanced isolation layer is interposed between the buried layer and well regions on which devices of the first and second circuits are formed, wherein the ion enhanced isolation layer is doped with impurities of a polarity type different from that of the buried layer.
    Type: Grant
    Filed: November 12, 2005
    Date of Patent: March 3, 2009
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Wei Liu, Jun Xiu Liu, Chi-Hsuen Chang, Tzu-Chiang Sung, Chung-I Chen, Rann-Shyan Yeh
  • Patent number: 7436043
    Abstract: A semiconductor device includes multiple low voltage N-well (LVNW) areas biased at different potentials and isolated from a substrate by a common N+ buried layer (NBL) and at least one high voltage N-well (HVNW) area. The LVNW areas are coupled to the common, subjacent NBL through a common P+ buried layer (PBL). The method for forming the substrate usable in a semiconductor device includes forming the NBL in a designated low voltage area of a negatively biased P-type semiconductor substrate, forming the PBL in a section of the NBL area by implanting P-type impurity ions such as indium into the PBL, and growing a P-type epitaxial layer over the PBL using conditions that cause the P-type impurity ions to diffuse into the P-type epitaxial layer such that the PBL extends into the NBL. Low-voltage P-well areas are also formed in the P-type epitaxial layer and contact the PBL.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: October 14, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Tzu-Chiang Sung, Chih Po Huang, Rann Shyan Yeh, Jun Xiu Liu, Chi-Hsuen Chang, Chung-I Chen
  • Publication number: 20080229874
    Abstract: A bicycle toe positioning device comprises a treadle having a main body which is formed with an axial hole, an axial rod and a bearing set. The treadle is further formed with a first clamping portion and a second clamping portion. A tightening unit has a first positioning end and a second positioning end. In assembly, the first clamping portion is buckled to a rib and a pair of wings of the first positioning end. The second clamping portion is secured to the second positioning end so that the treadle is secured to the toe positioning unit. The first clamping portion has a buckling block which is fixed to the treadle by using an pivotal rod. A spring is retained in the first clamping portion and an adjust unit serves to adjust the tightness of the buckling block.
    Type: Application
    Filed: March 21, 2007
    Publication date: September 25, 2008
    Inventor: Chung-I Chen
  • Publication number: 20080202283
    Abstract: A bicycle treadle device comprises a treadle having an axial hole at a center portion thereof; at least one control block being installed at the treadle near the locking sheet; the control block being installed to the treadle; the control block being formed by a main ring; a first protrusion and a second protrusion being protruded from the main ring which has different sizes. By rotating the control block, it can be adjusted so that one of the main ring, the first protrusion and the second protrusion to resist against the front locking sheet of the locking sheet to adjust the expansion of the front locking sheet. Furthermore an adjusting unit is used to change the tightness of the elastic unit of the locking sheet.
    Type: Application
    Filed: February 23, 2007
    Publication date: August 28, 2008
    Inventor: Chung-I Chen
  • Publication number: 20080121068
    Abstract: A bicycle pedal assembly includes a pedal body having a sleeve tube and front and rear protruding portions. A front clamping member is mounted rotatably on the front protruding portion, and is biased by a front biasing member to rotate toward the sleeve tube. A locking member is connected to the front protruding portion, and is operable to abut against the front clamping member so as to lock the latter against rotational movement. A rear clamping member is mounted rotatably on the rear protruding portion, and is biased by a rear biasing member to rotate toward the sleeve tube. An adjusting member is connected to the rear clamping member, and is operable to adjust the biasing force of the rear biasing member.
    Type: Application
    Filed: November 29, 2006
    Publication date: May 29, 2008
    Inventor: Chung-I Chen
  • Patent number: 7301185
    Abstract: A high-voltage transistor device with an interlayer dielectric (ILD) etch stop layer for use in a subsequent contact hole process is provided. The etch stop layer is a high-resistivity film having a resistivity greater than 10 ohm-cm, thus leakage is prevented and breakdown voltage is improved when driving a high voltage greater than 5V at the gate site. A method for fabricating the high-voltage device is compatible with current low-voltage device processes and middle-voltage device processes.
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: November 27, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-I Chen, Hsin Kuan, Zhi-Cheng Chen, Rann-Shyan Yeh, Chi-Hsuen Chang, Jun Xiu Liu, Tzu-Chiang Sung, Chia-Wei Liu, Jieh-Ting Cheng
  • Publication number: 20070235831
    Abstract: A semiconductor structure for isolating a first circuit and a second circuit of various operating voltages includes a first isolation ring surrounding the first and second circuits on a semiconductor substrate. A buried layer continuously extending underneath the first and second circuits is formed on the semiconductor substrate, wherein the buried layer interfaces with the first isolation ring for isolating the first and second circuits from a backside bias of the semiconductor substrate. An ion enhanced isolation layer is interposed between the buried layer and well regions on which devices of the first and second circuits are formed, wherein the ion enhanced isolation layer is doped with impurities of a polarity type different from that of the buried layer.
    Type: Application
    Filed: November 12, 2005
    Publication date: October 11, 2007
    Inventors: Chia-Wei Liu, Jun Liu, Chi-Hsuen Chang, Tzu-Chiang Sung, Chung-I Chen, Rann-Shyan Yeh
  • Publication number: 20070137432
    Abstract: A foldable pedal assembly includes: a pedal frame formed with left and right studs opposite to each other in an axial direction; a crank-connecting part including left and right wing units that define left and right recesses, respectively, the left and right studs extending into the left and right recesses and being pivoted to the left and right wing units, respectively; left and right urging members disposed in the left and right recesses to urge the pedal frame in a first direction transverse to the axial direction, and to urge the crank-connecting part in a second direction opposite to the first direction; a first limiting unit abutting against at least one of the left and right studs by urging action of the urging members; and a second limiting unit abutting against at least one of the left and right wing units by urging action of the urging members.
    Type: Application
    Filed: October 12, 2005
    Publication date: June 21, 2007
    Inventor: Chung-I Chen
  • Patent number: 7228761
    Abstract: A foldable pedal assembly includes: a pedal frame formed with left and right studs opposite to each other in an axial direction; a crank-connecting part including left and right wing units that define left and right recesses, respectively, the left and right studs extending into the left and right recesses and being pivoted to the left and right wing units, respectively; left and right urging members disposed in the left and right recesses to urge the pedal frame in a first direction transverse to the axial direction, and to urge the crank-connecting part in a second direction opposite to the first direction; a first limiting unit abutting against at least one of the left and right studs by urging action of the urging members; and a second limiting unit abutting against at least one of the left and right wing units by urging action of the urging members.
    Type: Grant
    Filed: October 12, 2005
    Date of Patent: June 12, 2007
    Inventor: Chung-I Chen
  • Patent number: 7205630
    Abstract: Method and apparatus for a semiconductor device including high voltage MOS transistors is described. A substrate is provided with a low voltage and a high voltage region separated one from the other. Isolation regions containing an insulator are formed including at least one formed within one of said wells within the high voltage region. The angle of the transition from the active areas to the isolation regions in the high voltage device region is greater than a predetermined angle, in some embodiments it is greater than 40 degrees from vertical. In some embodiments the isolation regions are formed using shallow trench isolation techniques. In alternative embodiments the isolation regions are formed using field oxide formed by local oxidation of silicon techniques.
    Type: Grant
    Filed: May 5, 2005
    Date of Patent: April 17, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Hsuen Chang, Jun Xiu Liu, Tsung-Yi Huang, Chung-I Chen, Tzu-Chiang Sung, Chih Po Huang, Rann Shyan Yeh
  • Patent number: 7196392
    Abstract: A semiconductor structure includes an isolation ring disposed on a semiconductor substrate, surrounding first and second circuit areas. A buried isolation layer is continuously extended through the first circuit area and the second circuit area, in the semiconductor substrate. The buried isolation layer interfaces with the isolation ring, thereby isolating the first and second circuit areas from a backside bias of the semiconductor substrate. An ion enhanced isolation layer separates the first well in the first circuit area and the second well in the second circuit areas from the isolation ring and the buried isolation layer, thereby preventing punch-through between the wells of the circuit areas and the buried isolation layer.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: March 27, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jun-Xiu Liu, Chi-Hsuen Chang, Tzu-Chiang Sung, Chung-I Chen, Chih Po Huang
  • Publication number: 20060162488
    Abstract: A bicycle pedal assembly includes a pedal unit and a cleat that is adapted to be connected fixedly to a shoe. The pedal unit includes a pedal body, and a pair of front and rear retaining members. The cleat includes an insert block confined between front and rear retaining members and spaced apart from the pedal body, and a pedal-engaging block connected removably to the insert block and abutting against the pedal body. The pedal-engaging block is made of a material that is softer than the pedal body.
    Type: Application
    Filed: January 4, 2005
    Publication date: July 27, 2006
    Inventor: Chung-I Chen
  • Publication number: 20060133189
    Abstract: A semiconductor device includes multiple low voltage N-well (LVNW) areas biased at different potentials and isolated from a substrate by a common N+ buried layer (NBL) and at least one high voltage N-well (HVNW) area. The LVNW areas are coupled to the common, subjacent NBL through a common P+ buried layer (PBL). The method for forming the substrate usable in a semiconductor device includes forming the NBL in a designated low voltage area of a negatively biased P-type semiconductor substrate, forming the PBL in a section of the NBL area by implanting P-type impurity ions such as indium into the PBL, and growing a P-type epitaxial layer over the PBL using conditions that cause the P-type impurity ions to diffuse into the P-type epitaxial layer such that the PBL extends into the NBL. Low-voltage P-well areas are also formed in the P-type epitaxial layer and contact the PBL.
    Type: Application
    Filed: December 21, 2004
    Publication date: June 22, 2006
    Inventors: Tzu-Chiang Sung, Chih Huang, Rann Shyan Yeh, Jun Xiu Liu, Chi-Hsuen Chang, Chung-I Chen
  • Publication number: 20060113627
    Abstract: A high-voltage transistor device with an interlayer dielectric (ILD) etch stop layer for use in a subsequent contact hole process is provided. The etch stop layer is a high-resistivity film having a resistivity greater than 10 ohm-cm, thus leakage is prevented and breakdown voltage is improved when driving a high voltage greater than 5V at the gate site. A method for fabricating the high-voltage device is compatible with current low-voltage device processes and middle-voltage device processes.
    Type: Application
    Filed: November 29, 2004
    Publication date: June 1, 2006
    Inventors: Chung-I Chen, Hsin Kuan, Zhi-Cheng Chen, Rann-Shyan Yeh, Chi-Hsuen Chang, Jun Liu, Tzu-Chiang Sung, Chia-Wei Liu, Jieh-Ting Chang
  • Patent number: D522414
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: June 6, 2006
    Inventor: Chung-I Chen