Abstract: A display device includes a substrate including a pixel region and a peripheral region. A plurality of pixels is disposed in the pixel region of the substrate. Each of the plurality of pixels includes a light emitting element. Data lines and scan lines are connected to each of the plurality of pixels. A power line is configured to supply power to the plurality of pixels. The power line includes a plurality of first conductive lines and a plurality of second conductive lines intersecting the plurality of first conductive lines. The plurality of second conductive lines is arranged in a region between adjacent light emitting elements of the plurality of pixels. At least some of the plurality of second conductive lines extend in a direction oblique to a direction of extension of the data lines or the scan lines.

Abstract: A detection method for a malicious domain name in a domain name system (DNS) and a detection device are provided. The method includes: obtaining network connection data of an electronic device; capturing log data related to at least one domain name from the network connection data; analyzing the log data to generate at least one numerical feature related to the at least one domain name; inputting the at least one numerical feature into a multi-type prediction model, which includes a first data model and a second data model; and predicting whether a malicious domain name related to a malware or a phishing website exists in the at least one domain name by the multi-type prediction model according to the at least one numerical feature.

Abstract: A microfluidic detection unit comprises at least one fluid injection section, a fluid storage section and a detection section. Each fluid injection section defines a fluid outlet; the fluid storage section is in gas communication with the atmosphere and defines a fluid inlet; the detection section defines a first end in communication with the fluid outlet and a second end in communication with the fluid inlet. A height difference is defined between the fluid outlet and the fluid inlet along the direction of gravity. When a first fluid is injected from the at least one fluid injection section, the first fluid is driven by gravity to pass through the detection section and accumulate to form a droplet at the fluid inlet, such that a state of fluid pressure equilibrium of the first fluid is established.

Abstract: A non-metal spring includes two non-metal elastic units connected to each other and formed between two non-metal terminal rings. Each of the non-metal elastic units includes two intermediate rings intersecting each other, thereby providing two cross portions. The cross portions of each of the non-metal elastic units divide each of the intermediate rings into a first portion and a second portion. The first portions of the intermediate rings of one of the non-metal elastic units are connected to one of the terminal rings. The second portions of the intermediate rings of another one of the non-metal elastic units are connected to a remaining one of the terminal rings. The first portions of the intermediate rings of each of the non-metal elastic units are connected to the second portions of the intermediate rings of an adjacent one of the non-metal elastic units.

Abstract: A semiconductor package includes a substrate; a substrate pad on the substrate; a first semiconductor chip and a second semiconductor chip on the substrate; a connective terminal between the substrate pad and the first semiconductor chip and between the substrate pad and the second semiconductor chip; a dummy pad on the substrate, and spaced apart from the substrate pad, wherein the dummy pad is between the first semiconductor chip and the second semiconductor chip; and an underfill material layer interposed between the substrate and the first semiconductor chip and between the substrate and the second semiconductor chip, wherein the dummy pad and the substrate pad include a same material.

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure includes the following. A gate structure is formed on a substrate. A tilt implanting process is performed to implant group IV elements into the substrate to form a doped region, and the doped region is located on two sides of the gate structure and partially located under the gate structure. A part of the substrate on two sides of the gate structure is removed to form a first recess. A cleaning process is performed on the surface of the first recess. A wet etching process is performed on the first recess to form a second recess. A semiconductor layer is formed in the second recess.

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

Abstract: A method for forming a shallow trench isolation (STI) structure using two individual STI trench etching processes is provided. A first STI etching process forms first trenches with one or more sizes in rows along a first dimension in a silicon substrate. A first dielectric is filled in the first trenches following a first thermal oxidation forming a first liner oxide surrounding the first trenches. A second STI trench etching process forms second trenches with one or more sizes in a second dimension to define active regions separated from each other by the first trenches filled with the first dielectric material and second trenches. A second dielectric is filled in the second trenches following a second thermal oxidation forming a second liner oxide surrounding the second trenches. Active region encroachment caused by the first and second thermal oxidation is reduced by doing the two individual STI trench etching processes.

Abstract: A method for forming a shallow trench isolation (STI) structure using two individual STI trench etching processes is provided. A first STI etching process forms first trenches with one or more sizes in rows along a first dimension in a silicon substrate. A first dielectric is filled in the first trenches following a first thermal oxidation forming a first liner oxide surrounding the first trenches. A second STI trench etching process forms second trenches with one or more sizes in a second dimension to define active regions separated from each other by the first trenches filled with the first dielectric material and second trenches. A second dielectric is filled in the second trenches following a second thermal oxidation forming a second liner oxide surrounding the second trenches. Active region encroachment caused by the first and second thermal oxidation is reduced by doing the two individual STI trench etching processes.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes: providing a semiconductor substrate comprising a memory region and a logic region; forming a memory gate in or on the memory region; forming a plurality of first poly-silicon gates on the memory region and surrounding the memory gate; and forming a plurality of second poly-silicon gates on the logic region simultaneously with the formation of the first poly-silicon gates.

Abstract: Processes to form differently-pitched gate structures are provided. An example method includes providing a workpiece having a substrate and semiconductor fins spaced apart from one another by an isolation feature, depositing a gate material layer over the workpiece, forming a patterned hard mask over the gate material layer, the patterned hard mask including differently-pitched elongated features, performing a first etch process using the patterned hard mask as an etch mask through the gate material layer to form a trench, performing a second etch process using the patterned hard mask as an etch mask to extend the trench to a top surface of the isolation feature, and performing a third etch process using the patterned hard mask to extend the trench into the isolation feature. The first etch process includes use of carbon tetrafluoride and is free of use of oxygen gas.

Abstract: A battery system, a control method of a cell balance procedure and a calculation method of a balance charge capacity are provided. The battery system includes a plurality of battery units, a communication bus and a host control unit. Each battery unit includes a plurality of cells, an isolated charger, a switch array circuit, a balance slave switch and a balance slave controller. The host control unit includes a balance host controller, a balance host switch and a system current measurement unit. When the error between a balance detection voltage calculated by each balance slave controller and the balance detection voltage calculated by the balance host controller is less than a predetermined value, the balance host switch and the corresponding balance slave switches are in conduction and the specified plurality cells of battery system are charged for keeping cell balance purpose.

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

Abstract: A battery system includes several unit battery groups, a main switch, a current measuring unit, several slave control units and a master control unit. Each unit battery group includes several cells. The main switch and the current measuring unit are serially connected to the unit battery groups. The current measuring unit measures a measured system current value of the unit battery groups. The slave control units are electrically connected to the unit battery groups respectively. Each slave control unit measures a physical parameter value of each cell in each unit battery group. The master control unit communicates with the slave control units to: disconnect the main switch when the abnormality determined according to the physical parameter value or the measured system current value pertains to system abnormality; and, perform a processing procedure for detection abnormality when the abnormality pertains to detection abnormality.

Abstract: A method for forming a shallow trench isolation (STI) structure using two individual STI trench etching processes is provided. A first STI etching process forms first trenches with one or more sizes in rows along a first dimension in a silicon substrate. A first dielectric is filled in the first trenches following a first thermal oxidation forming a first liner oxide surrounding the first trenches. A second STI trench etching process forms second trenches with one or more sizes in a second dimension to define active regions separated from each other by the first trenches filled with the first dielectric material and second trenches. A second dielectric is filled in the second trenches following a second thermal oxidation forming a second liner oxide surrounding the second trenches. Active region encroachment caused by the first and second thermal oxidation is reduced by doing the two individual STI trench etching processes.

Abstract: A semiconductor device includes an insulating layer on a substrate; a via extending from within the substrate and extending through one face of the substrate and a bottom face of a trench defined in the insulating layer such that a portion of a sidewall and a top face of the via are exposed through the substrate; and a pad contacting the exposed portion of the sidewall and the top face of the via. The pad fills the trench. The insulating layer includes a passivation layer on the substrate, and a protective layer is on the passivation layer. An etch stop layer is absent between the passivation layer and the protective layer. A vertical level of a bottom face of the trench is higher than a vertical level of one face of the substrate and is lower than a vertical level of a top face of the passivation layer.

Abstract: A device includes a plurality of fin structures that each protrude vertically upwards out of a substrate and each extend in a first direction in a top view. A gate structure is disposed over the fin structures. The gate structure extends in a second direction in the top view. The second direction is different from the first direction. The fin structures have a fin pitch equal to a sum of: a dimension of one of the fin structures in the second direction and a distance between an adjacent pair of the fin structures in the second direction. An end segment of the gate structure extends beyond an edge of a closest one of the fin structures in the second direction. The end segment has a tapered profile in the top view or is at least 4 times as long as the fin pitch in the second direction.

Abstract: A battery module includes a housing, at least one cell stack inside the housing, a tightening assembly and a thermal conductive element. The tightening assembly includes first and second plugin members. The first plugin member has a first stopping portion and a first bolt portion connected with the first stopping portion, and the first bolt portion is tapered from the first stopping portion. The second plugin member has a second stopping portion and a second bolt portion connected with the second stopping portion, and the second bolt portion is tapered from the second stopping portion. The first and second plugin members are detachably inserted into the battery module from two opposing sides of the cell stack. The thermal conductive element tightens the cell stack to the housing.

Abstract: A device includes a plurality of fin structures that each protrude vertically upwards out of a substrate and each extend in a first direction in a top view. A gate structure is disposed over the fin structures. The gate structure extends in a second direction in the top view. The second direction is different from the first direction. The fin structures have a fin pitch equal to a sum of: a dimension of one of the fin structures in the second direction and a distance between an adjacent pair of the fin structures in the second direction. An end segment of the gate structure extends beyond an edge of a closest one of the fin structures in the second direction. The end segment has a tapered profile in the top view or is at least 4 times as long as the fin pitch in the second direction.