Patents by Inventor CHUNG In-Sun

CHUNG In-Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8050061
    Abstract: A control circuit for a switching power supply (SPS) includes power input and output interfaces, a relay, a relay driving circuit, a microprocessor, and an alternating current/directing current (AC/DC) converter. The power input interface receives an external alternating current (AC) power signal, and transmits the AC power signal to the SPS via the power output interface. The AC/DC converter transforms the AC power signal into a direct current (DC) power signal to supply for the relay, the relay driving circuit, and the microprocessor. When a computer is turned on, the microprocessor sends a first control signal to control the relay driving circuit to drive the relay to connect the power input and output interfaces. When the computer is turned off, the microprocessor sends a second control signal to control the relay driving circuit to drive the relay to cut off connection between the power input and output interfaces.
    Type: Grant
    Filed: April 2, 2009
    Date of Patent: November 1, 2011
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Fang-Ta Tai, Chen-Hsiang Lin, Teng-Feng Zou, Jui-Ting Hung, Yi-Bin Hwang, Li-Chung Sun
  • Publication number: 20110119912
    Abstract: A method for manufacturing a tape wiring board in accordance with the present invention may employ an imprinting process in forming a wiring pattern, thereby reducing the number of processes for manufacturing a tape wiring board and allowing the manufacturing process to proceed in a single production line. Therefore, the manufacturing time and cost may he reduced. A profile of the wiring pattern may be determined by the shape of an impression pattern of a mold. This may establish the top width of inner and outer leads and incorporate tine pad pitch. Although ILB and OLB process may use an NCP, connection reliability may be established due to the soft and elastic wiring pattern.
    Type: Application
    Filed: February 2, 2011
    Publication date: May 26, 2011
    Inventors: Kyoung-Sei Choi, Sa-Yoon Kang, Yong-Hwan Kwon, Chung-Sun Lee
  • Patent number: 7948555
    Abstract: A camera module includes an image sensor chip, a lens structure, a transparent substrate, an adhesive portion, and a light blocking layer. The image sensor chip includes a light receiving area and a circuit area. The lens structure is positioned on the image sensor chip and configured to allow light to enter the image sensor chip. The transparent substrate is positioned between the image sensor chip and the lens structure, the transparent substrate allowing light from the lens structure to enter the light receiving area. The adhesive portion attaches the image sensor chip and the transparent substrate, and covers the circuit area. The light blocking layer is attached to the transparent substrate to block light from entering the circuit area.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: May 24, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hwan Kwon, Un-Byoung Kang, Chung-Sun Lee, Woon-Seong Kwon, Hyung-Sun Jang
  • Publication number: 20110115459
    Abstract: A phase adjusting system includes a controlled element, a multi-phase pulse-width modulation (PWM) controller comprising default and non-default phases, and a microprogrammed control unit (MCU). The PWM controller provides phases to the controlled element. The MCU is connected to the controlled element via the multi-phase PWM controller. The MCU detects the work voltage level of the controlled element and controls the multi-phase PWM controller to provide a corresponding number of phases to the controlled element. The MCU determines whether work time of the default phases of the multi-phase PWM controller is greater than a predetermined value in response to the MCU being initialized. The default phases are changed to non-default phases and a corresponding number of the plurality of non-default phases are changed to default phases in response to the work time of the plurality of default phases of the multi-phase PWM controller being greater than the predetermined value.
    Type: Application
    Filed: December 8, 2009
    Publication date: May 19, 2011
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: CHIH-SHENG HSIEH, LI-CHUNG SUN
  • Publication number: 20110075369
    Abstract: An electronic device including a heat generation element, a heat dissipation plate, and a heat pipe is provided. The heat dissipation plate includes a top surface, a bottom surface, a pair of longitudinal side surfaces, and a pair of lateral side surfaces including a third side surface and a fourth side surface. The longitudinal side surfaces include first and second side surfaces. The lateral side surfaces include third and fourth side surfaces. The first, second, third and fourth side surfaces are connected to both the top surface and the bottom surface. The heat pipe is disposed in contact with the heat dissipation plate, and the heat pipe and the heat generation element are disposed on the bottom surface of the heat dissipation plate. The heat pipe is disposed on the heat dissipation plate and extension of the heat pipe is not beyond the first, second, third and fourth side surfaces.
    Type: Application
    Filed: January 8, 2010
    Publication date: March 31, 2011
    Applicant: INVENTEC CORPORATION
    Inventors: Kuang-Chung Sun, Ting-Chiang Huang, Chiun-Peng Chen, Chih-Kuang Chung, Sheng-Chieh Hsu, Wei-Yi Lin
  • Patent number: 7895742
    Abstract: A method for manufacturing a tape wiring board in accordance with the present invention may employ an imprinting process in forming a wiring pattern thereby reducing the number of processes for manufacturing a tape wiring board and allowing the manufacturing process to proceed in a single production line. Therefore, the manufacturing time and cost may be reduced. A profile of the wiring pattern may be determined by the shape of an impression pattern of a mold. This may establish the top width of inner and outer leads and incorporate fine pad pitch. Although ILB and OLB process may use an NCP, connection reliability may be established due to the soft and elastic wiring pattern.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: March 1, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Sei Choi, Sa-Yoon Kang, Yong-Hwan Kwon, Chung-Sun Lee
  • Patent number: 7893514
    Abstract: An image sensor package, a method of manufacturing the same, and an image sensor module including the image sensor package are provided. In the image sensor package, an image sensor chip is installed onto a depression of a transmissive substrate. An adhesive bonds the image sensor chip to the transmissive substrate and seals an Active Pixel Sensor (APS) on the image sensor chip, protecting it from fine particle contamination. An IR cutting film is disposed on the transmissive substrate to minimize the height of the image sensor package. The image sensor package is electrically connected to external connection pads in the depression. Consequently, the image sensor package has a minimum height, is not susceptible to particle contamination, and does not require expensive alignment processes during manufacturing.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: February 22, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woon-Seong Kwon, Yong-Hwan Kwon, Un-Byoung Kang, Chung-Sun Lee, Hyung-Sun Jang
  • Patent number: 7884392
    Abstract: One embodiment exemplarily described herein can be characterized as an image sensor including a substrate having a front surface and a rear surface; a photoelectric converting portion on the front surface of the substrate; a through via extending through the substrate, wherein the through via is electrically connected to the photoelectric converting portion; an external connection terminal on the rear surface of the substrate, wherein the external connection terminal is connected to the through via; and a light shading layer formed on a portion of the rear surface of the substrate, wherein the light shading layer is substantially opaque with respect to an external light. In some embodiments, the portion of the rear surface of the substrate on which the light shading layer is formed is not overlapped by the through via or the external connection terminal.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: February 8, 2011
    Inventors: Hyuek-Jae Lee, Tae-Je Cho, Yong-Hwan Kwon, Un-Byoung Kang, Chung-Sun Lee, Woon-Seong Kwon, Hyung-Sun Jang
  • Publication number: 20100320500
    Abstract: A method of manufacturing a semiconductor device includes forming a diffusion barrier layer on a substrate, and forming at least two features on the substrate such that the diffusion barrier layer is respectively disposed between each feature and the substrate and contacts the at least two features. A first impurity region of the substrate contains impurities of a first type, a second impurity region of the substrate contains impurities of a second type, different from the first type, a first feature of the at least two features is in the first impurity region, and a second feature of the at least two features is in the second impurity region, such that the second feature is electrically isolated from first feature by the different impurity regions.
    Type: Application
    Filed: August 30, 2010
    Publication date: December 23, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: UN BYOUNG KANG, Yong Hwan Kwon, Chung Sun Lee, Woon Seong Kwon, Hyung Sun Jang
  • Publication number: 20100284206
    Abstract: A power adapter for an electronic device selectively works in different modes according to a working state signal of the electronic device. When the electronic device is powered off or on with a battery in a determined charge state, the power adapter controls a relay to turn off the relay to disconnect power to the electronic device.
    Type: Application
    Filed: June 8, 2009
    Publication date: November 11, 2010
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: FANG-TA TAI, CHEN-HSIANG LIN, LI-CHUNG SUN, TENG-FENG ZOU, JUI-TING HUNG, YI-BIN HWANG
  • Publication number: 20100220506
    Abstract: A control circuit for a switching power supply (SPS) includes power input and output interfaces, a relay, a relay driving circuit, a microprocessor, and an alternating current/directing current (AC/DC) converter. The power input interface receives an external alternating current (AC) power signal, and transmits the AC power signal to the SPS via the power output interface. The AC/DC converter transforms the AC power signal into a direct current (DC) power signal to supply for the relay, the relay driving circuit, and the microprocessor. When a computer is turned on, the microprocessor sends a first control signal to control the relay driving circuit to drive the relay to connect the power input and output interfaces. When the computer is turned off, the microprocessor sends a second control signal to control the relay driving circuit to drive the relay to cut off connection between the power input and output interfaces.
    Type: Application
    Filed: April 2, 2009
    Publication date: September 2, 2010
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Fang-Ta Tai, Chen-Hsiang Lin, Teng-Feng Zou, Jui-Ting Hung, Yi-Bin Hwang, Li-Chung Sun
  • Patent number: 7786581
    Abstract: A method of manufacturing a semiconductor device includes forming a diffusion barrier layer on a substrate, and forming at least two features on the substrate such that the diffusion barrier layer is respectively disposed between each feature and the substrate and contacts the at least two features. A first impurity region of the substrate contains impurities of a first type, a second impurity region of the substrate contains impurities of a second type, different from the first type, a first feature of the at least two features is in the first impurity region, and a second feature of the at least two features is in the second impurity region, such that the second feature is electrically isolated from first feature by the different impurity regions.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: August 31, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Un Byoung Kang, Yong Hwan Kwon, Chung Sun Lee, Woon Seong Kwon, Hyung Sun Jang
  • Publication number: 20100213621
    Abstract: Method for increasing the moisture-proof capability of a chip includes coating moisture-proof glue at the chink of the chip. More particularly, when the packaging structure carries a chink exposed to outside of the chip, the chink is coated with the moisture-proof glue for preventing moisture from entering the internal part of the chip so as to increase the moisture-proof capability of the chip.
    Type: Application
    Filed: January 20, 2010
    Publication date: August 26, 2010
    Inventors: Wei-Chung Sun, Chin-Ming Lin, Wei-Jen Chen, Chin-Feng Wu
  • Publication number: 20100072948
    Abstract: A characteristic tracking method for a battery module including at least one battery is disclosed. A look-up table is provided according to a primary characteristic of the battery. It is determined whether a battery has satisfied a preset condition when the battery module is operated from a usage state to an idling state. The battery is measured to have obtained a first voltage and a real capacity when the battery satisfies the preset condition. The measured first voltage is utilized to locate a table capacity of the battery from the look-up table. The look-up table is updated according to the real capacity and the table capacity. A peripheral circuit of characteristic tracking method has been exhibited.
    Type: Application
    Filed: July 2, 2009
    Publication date: March 25, 2010
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chein-Chung SUN, Yuh-Fwu Chou, Ming-Wang Cheng, Sheng-Yong Shen
  • Patent number: 7673194
    Abstract: An apparatus for generating a function activation signal to activate a function in an integrated circuit device comprises a power-on circuit receiving a power input and initializing and generating a test activation signal, a test circuit receiving the test activation signal and generating a test result signal, and a threshold decision circuit receiving the test result signal and generating the function activation signal. The test circuit models a function of the integrated circuit device and generates the test result signal when the power input has reached a sufficient voltage to perform the function of the integrated circuit device. The threshold decision circuit generates the function activation signal if the test result signal indicates the power input has reached a sufficient voltage to perform the function of the integrated circuit device.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: March 2, 2010
    Assignee: Actel Corporation
    Inventors: Chung Sun, Eddy Huang, Stephen Chan
  • Publication number: 20100019338
    Abstract: A stack type semiconductor chip package includes a first wafer mold, a protection substrate, and a second wafer mold that are stacked in a wafer level process. The first wafer mold includes a first chip having first pads and a first mold layer encapsulating the first chip. The protection substrate is placed on the first wafer mold, is mechanically bonded with the first wafer mold using a first adhesive layer, and includes wiring layers facing the first pads. The second wafer mold is placed under the first wafer mold, is mechanically bonded with the first wafer mold using a second adhesive layer, and includes a second chip having second pads, and a second mold layer encapsulating the second chip. First vias electrically connect the wiring layers of the protection substrate with the second pads. Second vias electrically connect the wiring layers of the protection substrate with external connection terminals.
    Type: Application
    Filed: October 7, 2009
    Publication date: January 28, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Woon-Seong KWON, Yong-Hwan KWON, Un-Byoung KANG, Chung-Sun LEE, Hyung-Sun JANG
  • Patent number: 7619315
    Abstract: A stack type semiconductor chip package includes a first wafer mold, a protection substrate, and a second wafer mold that are stacked in a wafer level process. The first wafer mold includes a first chip having first pads and a first mold layer encapsulating the first chip. The protection substrate is placed on the first wafer mold, is mechanically bonded with the first wafer mold using a first adhesive layer, and includes wiring layers facing the first pads. The second wafer mold is placed under the first wafer mold, is mechanically bonded with the first wafer mold using a second adhesive layer, and includes a second chip having second pads, and a second mold layer encapsulating the second chip. First vias electrically connect the wiring layers of the protection substrate with the second pads. Second vias electrically connect the wiring layers of the protection substrate with external connection terminals.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: November 17, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woon-Seong Kwon, Yong-Hwan Kwon, Un-Byoung Kang, Chung-Sun Lee, Hyung-Sun Jang
  • Publication number: 20090256931
    Abstract: A camera module, a method of manufacturing the same, and an electronic system having the same are provided. The camera module includes an image sensor chip having an active plane and a backside, a ground wiring extending from a sidewall of the image sensor chip to the backside, a lens structure having a light detector with at least one lens stacked on the active plane, and a conductive housing extending to the ground wiring along with an outer wall of the lens structure excluding the light detector.
    Type: Application
    Filed: March 12, 2009
    Publication date: October 15, 2009
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Chung-Sun Lee, Yong-Hwan Kwon, Un-Byoung Kang, Hyuek-Jae Lee, Woon-Seong Kwon, Hyung-Sun Jang
  • Publication number: 20090200632
    Abstract: One embodiment exemplarily described herein can be characterized as an image sensor including a substrate having a front surface and a rear surface; a photoelectric converting portion on the front surface of the substrate; a through via extending through the substrate, wherein the through via is electrically connected to the photoelectric converting portion; an external connection terminal on the rear surface of the substrate, wherein the external connection terminal is connected to the through via; and a light shading layer formed on a portion of the rear surface of the substrate, wherein the light shading layer is substantially opaque with respect to an external light. In some embodiments, the portion of the rear surface of the substrate on which the light shading layer is formed is not overlapped by the through via or the external connection terminal.
    Type: Application
    Filed: January 29, 2009
    Publication date: August 13, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyuek-Jae LEE, Tae-Je CHO, Yong-Hwan KWON, Un-Byoung KANG, Chung-Sun LEE, Woon-Seong KWON, Hyung-Sun JANG
  • Patent number: 7569423
    Abstract: A wafer-level-chip-scale package and related method of fabrication are disclosed. The wafer-level-chip-scale package comprises a semiconductor substrate comprising an integrated circuit, a conductive ball disposed on the semiconductor substrate and electrically connected to the integrated circuit, and a protective portion formed from an insulating material and disposed on bottom and side surfaces of the semiconductor substrate.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: August 4, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-hwan Kwon, Chung-sun Lee, Woon-byung Kang