Abstract: Circuits and methods for providing a floating gate structure comprising floating gate cells having improved reverse tunnel disturb immunity. A floating gate structure is formed over a semiconductor substrate comprising a floating gate, a charge trapping dielectric layer is formed, and a control gate is formed. The floating gate structure has vertical sidewalls, one side adjacent a source region and one side adjacent a drain region. A symmetric sidewall dielectric is formed over the floating gate structure on both the source side and drain side regions. An asymmetric dielectric layer is formed over the drain side sidewall only. The use of the asymmetric sidewall on the drain side sidewall provides improved RTD immunity. Methods for forming the structure are disclosed.

Abstract: Circuits and methods for providing a floating gate structure comprising floating gate cells having improved reverse tunnel disturb immunity. A floating gate structure is formed over a semiconductor substrate comprising a floating gate, a charge trapping dielectric layer is formed, and a control gate is formed. The floating gate structure has vertical sidewalls, one side adjacent a source region and one side adjacent a drain region. A symmetric sidewall dielectric is formed over the floating gate structure on both the source side and drain side regions. An asymmetric dielectric layer is formed over the drain side sidewall only. The use of the asymmetric sidewall on the drain side sidewall provides improved RTD immunity. Methods for forming the structure are disclosed.