Abstract: A method and apparatus for providing a charge pump that is particularly useful for generating high voltages and high currents for erasing and programming flash electrically-erasable programmable read only memory arrays (Flash EEPROMs). The invention includes an efficient method and circuit for generating a pumped voltage with no voltage drop from one stage to the next by using a simple two-phase clocking scheme and an auxiliary pump to gate a larger primary pump. One feature allows adjustment of the level of voltage pumping to accommodate higher voltage power supplies.

Abstract: A method and apparatus for providing a charge pump that is particularly useful for generating high voltages and high currents for erasing and programming flash electrically-erasable programmable read only memory arrays (Flash EEPROMs). The invention includes an efficient method and circuit for generating a pumped voltage with no voltage drop from one stage to the next by using a simple two-phase clocking scheme and an auxiliary pump to gate a larger primary pump. One feature allows adjustment of the level of voltage pumping to accommodate higher voltage power supplies.

Abstract: A low supply voltage negative charge pump for generating a relatively high negative voltage to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure includes charge pump means (210) formed of a plurality of charge pump stages (201-206) and coupling capacitor means (C201-C212) for delivering clock signals to the plurality of charge pump stages. Each of the plurality of charge pump stages is formed of an N-channel intrinsic pass transistor (N1-N6), an N-channel intrinsic initialization transistor (MD1-MD6), and an N-channel intrinsic precharge transistor (MX3-MX7, MX1) which are disposed in separate p-wells so as to reduce body effect. As a result, the negative charge pump is operable using a supply voltage of +3 volts or lower.

Abstract: A flash memory device is divided into two or more banks. Each bank includes a number of sectors. Each sector includes flash memory cells. Each bank has a decoder that selectively receives an address from an input address buffer or from an internal address sequencer controlled by an internal state machine. The output data for each bank can be communicated to a read sense amplifier or a verify sense amplifier. The read sense amplifier connects to the output buffer while the verify sense amplifier connects to the state machine. When one bank receives a write command, the internal state machine takes control and starts the program or erase operation. While one bank is busy with a program or erase operation, the other bank can be accessed for a read operation. Power is supplied for each of the read and write operations via an internal multiplexed multi power supply source that provides an amount of power needed based on the memory operation being performed.

Abstract: A timing apparatus for monitoring when a memory array in a non-volatile storage device needs to be refreshed includes a programmable semiconductor device and detecting means for detecting when the amount of charge on the programmable semiconductor device has diminished to at most a threshold amount. In one embodiment, the programmable semiconductor device is a floating gate transistor programmed by adding charge to the floating gate. The detecting means monitors the I.sub.DS current of the transistor and determines an array refresh time when more than a negligible amount of I.sub.DS current is detected.

Abstract: A non-volatile memory that allows simultaneous reading and writing operations by time multiplexing a single x-decode path between read and write operations. This is accomplished using appropriate timing signals to store/latch a first word line for a first operation and then relinquishing the x-decode path so that a second operation can load an address and access a second word line.

Abstract: A programming algorithm for a flash memory wherein programming circuitry is subdivided into a set of separately controllable groups. The algorithm detects a number of logic zeros to be programmed into a flash cell array by each group and switches among the groups such that a number of simultaneously programmed cells in the flash cell array does not exceed a predetermined number and such that maximum available programming current is used to enhance programming speed.

Abstract: A low supply voltage negative charge pump for generating a relatively high negative voltage to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure includes charge pump means (210) formed of a plurality of charge pump stages (201-206) and coupling capacitor means (C201-C212) for delivering clock signals to the plurality of charge pump stages. Each of the plurality of charge pump stages is formed of an N-channel intrinsic pass transistor (N1-N6), an N-channel intrinsic initialization transistor (MD1-MD6), and an N-channel intrinsic precharge transistor (MX3-MX7, MX1) which are disposed in separate p-wells so as to reduce body effect. As a result, the negative charge pump is operable using a supply voltage of +3 volts or lower.

Abstract: A method for correcting over-corrected memory cells in a flash EPROM. The flash EPROM includes an array of memory cells (25), where each of the cells includes a gate 18, a floating gate (16), a source (12), a drain (14), and a substrate (10). The method includes bulk erasing each of cells in the array of cells (step 40), which results in a plurality of over-erased cells. The over-erased cells are then corrected (step 42), which results in a plurality of over-corrected cells. The over-corrected cells are identified (step 44) and selectively erased (step 46), such that a uniform threshold voltage distribution (54) is provided for the cells in the flash EPROM.

Abstract: There is provided an improved method for eliminating of cycling-induced electron trapping in the tunneling oxide of flash EEPROM devices. A relatively low positive pulse voltage is applied to a source region of the EEPROM devices during an entire erase cycle. Simultaneously, a negative ramp voltage is applied to a control gate of the EEPROM devices during the entire erase cycle so as to accomplish an averaging tunneling field from the beginning of the erase cycle to the end of the erase cycle.

Abstract: A distributed negative gate power supply for generating and selectively supplying a relatively high negative voltage to control gates of memory cells in selected half-sectors via wordlines in an array of flash EEPROM memory cells during flash erasure. The distributed negative gate power supply includes a main charge pumping circuit (20a, 20b), a plurality of distribution sector pumping means (18a-18p). Each of the plurality of distribution sector pumping circuits is responsive to a half-sector select signal for selectively connecting the primary negative voltage to the wordlines of the selected half-sectors.

Abstract: A power-on reset circuit for generating and maintaining a reset signal in an active low state during power-up until a power supply voltage exceeds a predetermined level includes a resetting circuit (12a) and a control logic circuit (12b). The reset circuit is responsive to a monitoring signal, a start-up signal and a reference voltage for generating a reset signal which is initially in the active low state. The reset circuit includes a differential comparator (54) having a first input for receiving the start-up signal, a second input for receiving the reference voltage, and an output for generating the reset signal. The control logic circuit is responsive to the monitoring signal and the reset signal for generating a logic control signal which is initially in a high state. The differential comparator is responsive to the control signal and is activated only after the power supply voltage has exceeded a predetermined level so as to maintain initially the reset signal on its output in the low state.

Abstract: An improved architecture for an array of flash EEPROM cells with paged erase is provided. The array is formed of a plurality of half-sectors. In each sector, the sources of the memory cell transistors are connected to a separate individual ground line. A ground line circuit is provided for generating a half-sector ground line signal. The separate individual ground line is connected to the ground line circuit for receiving the half-sector ground line signal which is at a predetermined positive potential during erase.

Abstract: An improved over-erased bit correction structure is provided for performing a correction operation on over-erased memory cells in an array of flash EEPROM memory cells after erase operation so as to render high endurance. Sensing circuitry (20) is used to detect column leakage current indicative of an over-erased bit during an APDE mode of operation and for generating a logic signal representative of data stored in the memory cell. A data input buffer circuit (26) is used to compare the logic signal and a data signal representative of data programmed in the memory cell so as to generate a bit match signal. A pulse counter (30) is coupled to the data input buffer circuit for counting a plurality of programming pulses applied thereto.

Abstract: An improved redundancy architecture is provided for an array of flash EEPROM cells which permit repair of defective columns of memory cells in the array with redundant columns of memory cells on a sector-by-sector basis. The redundancy circuitry includes a plurality of sector-based redundancy blocks (2-8) each having redundant columns of memory cells extending through the plurality of sectors. Sector selection transistors (Q1,Q2) are provided for dividing the redundant columns into different segments, each residing in at least one of the plurality of sectors and for isolating the different segments so as to allow independent use from other segments in the same redundant column in repairing defective columns in the corresponding ones of the plurality of sectors.

Abstract: A positive power supply for generating and supplying a regulated positive potential to control gates of selected memory cells via word lines in an array of flash EEPROM memory cells during programming includes a clock circuit (18b) for generating a pair of non-overlapping clock signals and charge pump means (18c) responsive to an external power supply potential (VCC) and to the non-overlapping clock signals for generating a high positive voltage. A regulator circuit (20) responsive to the high positive voltage and a reference voltage is provided for controlling the regulated positive potential so that it is independent of the external power supply potential (VCC).

Abstract: A negative power supply for generating and supplying a regulated negative potential to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure includes charge pumping means (12) formed of a plurality of charge pump stages (401-404) for generating a high negative voltage, and cancellation means coupled to each stage of the charge pump means for effectively canceling out threshold voltage drops in the charge pump means. A regulator means (16) responsive to the high negative voltage and a reference potential is provided for generating the regulated negative potential so that it is independent of an external supply potential (VCC).

Abstract: A drain power supply for generating and supplying a regulated positive potential to drain regions of selected memory cells via bit lines in an array of flash EEPROM memory cells during programming includes charge pump means (20) formed of a plurality of charge pump sections (20a-20h) driven by one of a plurality of staggered clock signals for generating a moderately high level positive voltage. Cancellation means (26, 28) are coupled to each of the plurality of charge pump sections for effectively canceling out threshold voltage drops in the charge pump circuit. A regulator circuit (22) responsive to the regulated positive potential at an output node and a reference voltage is provided for generating a control voltage so as to control the high level positive voltage on the output node.