Abstract: A semiconductor device with active junction area determined by the surface of the floor of a hole etched into a body of semiconductor material. A body of highly doped semiconductor material is overlayed with two layers of semiconductor material of the same conductivity type. The layer in contact with the highly doped body is moderately doped while the upper layer is very lightly doped. A hole is etched through the top layer extending slightly into the moderately doped layer. A Schottky barrier contact is plated throughout the etched region. The total parasitic capacitance of such devices is much lower than that of prior art devices and the reverse breakdown characteristics are improved.

Abstract: A process of forming a composite semiconductor integrated circuit by forming one or more epitaxial layers of semiconductor material on a semiconductor substrate, forming pedestals by etching partially through said epitaxial layers to form regions projecting from said substrate and etching through said epitaxial layers to form stress relieving channels in the substrate surrounding the pedestals. A thick layer of easily removable material such as an evaporated layer of chromium plus gold and a plated layer of gold is deposited of sufficient thickness to provide good mechanical support, and the substrate is removed by lapping, grinding or etching until at least the stress relieving channels are exposed thereby forming separate semiconductor elements containing said epitaxial regions.

Abstract: A method of hermetically sealing semiconductor devices utilizes a dielectric tube with a two step structure at one end. The tube is used to surround a semiconductor. The two step end of the tube is metallized. The other end of the tube is flat and is brazed onto a metal stud so that the semiconductor is in the center of the brazed joint. A metal lid is painted with a conductive material and then placed into a rim formed by the two step end. When the paint dries, a metal layer is electrodeposited at the top of the lid and tube.

Abstract: A process of forming a composite semiconductor integrated circuit by forming one or more epitaxial layers of semiconductor material on a semiconductor substrate, forming pedestals by etching partially through said epitaxial layers to form regions projecting from said substrate and etching through said epitaxial layers to form stress relieving channels in the substrate surrounding the pedestals. A thick layer of easily removable material such as an evaporated layer of chromium plus gold and a plated layer of gold is deposited of sufficient thickness to provide good mechanical support, and the substrate is removed by lapping, grinding or etching until at least the stress relieving channels are exposed thereby forming separate semiconductor elements containing said epitaxial regions.