Patents by Inventor Chung Kwang Christopher TAN

Chung Kwang Christopher TAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11929330
    Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Kristof Darmawikarta, Hiroki Tanaka, Robert May, Sameer Paital, Bai Nie, Jesse Jones, Chung Kwang Christopher Tan
  • Publication number: 20240071777
    Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, a method for forming an IC package support may include forming a first dielectric material having a surface; forming a first conductive via in the first dielectric material, wherein the first conductive via has tapered sidewalls with an angle that is equal to or less than 80 degrees relative to the surface of the first dielectric material; forming a second dielectric material, having a surface, on the first dielectric material; and forming a second conductive via in the second dielectric material, wherein the second conductive via is electrically coupled to the first conductive via, has tapered sidewalls with an angle that is greater than 80 degrees relative to the surface of the second dielectric material, and a maximum diameter between 2 microns and 20 microns.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicant: Intel Corporation
    Inventors: Kristof Kuwawi Darmawikarta, Robert May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Chung Kwang Christopher Tan, Aleksandar Aleksov
  • Patent number: 11854834
    Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: December 26, 2023
    Assignee: Intel Corporation
    Inventors: Kristof Kuwawi Darmawikarta, Robert May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Chung Kwang Christopher Tan, Aleksandar Aleksov
  • Patent number: 11676891
    Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: June 13, 2023
    Assignee: Intel Corporation
    Inventors: Hongxia Feng, Dingying David Xu, Sheng C. Li, Matthew L. Tingey, Meizi Jiao, Chung Kwang Christopher Tan
  • Publication number: 20230022714
    Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.
    Type: Application
    Filed: September 29, 2022
    Publication date: January 26, 2023
    Inventors: Hongxia Feng, Dungying David Xu, Sheng C. Li, Matthew L. Tingey, Meizi Jiao, Chung Kwang Christopher Tan
  • Publication number: 20220223527
    Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.
    Type: Application
    Filed: April 4, 2022
    Publication date: July 14, 2022
    Inventors: Kristof DARMAWIKARTA, Hiroki TANAKA, Robert MAY, Sameer PAITAL, Bai NIE, Jesse JONES, Chung Kwang Christopher TAN
  • Publication number: 20220181166
    Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.
    Type: Application
    Filed: February 22, 2022
    Publication date: June 9, 2022
    Applicant: Intel Corporation
    Inventors: Kristof Kuwawi Darmawikarta, Robert May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Chung Kwang Christopher Tan, Aleksandar Aleksov
  • Patent number: 11322444
    Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: May 3, 2022
    Assignee: Intel Corporation
    Inventors: Kristof Darmawikarta, Hiroki Tanaka, Robert May, Sameer Paital, Bai Nie, Jesse Jones, Chung Kwang Christopher Tan
  • Patent number: 11309192
    Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: April 19, 2022
    Assignee: Intel Corporation
    Inventors: Kristof Kuwawi Darmawikarta, Robert May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Chung Kwang Christopher Tan, Aleksandar Aleksov
  • Publication number: 20210327800
    Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.
    Type: Application
    Filed: June 30, 2021
    Publication date: October 21, 2021
    Inventors: Hongxia FENG, Dingying David XU, Sheng C. LI, Matthew L. TINGEY, Meizi JIAO, Chung Kwang Christopher TAN
  • Patent number: 11088062
    Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: August 10, 2021
    Assignee: Intel Corporation
    Inventors: Hongxia Feng, Dingying David Xu, Sheng C. Li, Matthew L. Tingey, Meizi Jiao, Chung Kwang Christopher Tan
  • Publication number: 20190371621
    Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.
    Type: Application
    Filed: June 5, 2018
    Publication date: December 5, 2019
    Applicant: Intel Corporation
    Inventors: Kristof Kuwawi Darmawikarta, Robert May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Chung Kwang Christopher Tan, Aleksandar Aleksov
  • Publication number: 20190295951
    Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.
    Type: Application
    Filed: March 23, 2018
    Publication date: September 26, 2019
    Inventors: Kristof DARMAWIKARTA, Hiroki TANAKA, Robert MAY, Sameer PAITAL, Bai NIE, Jesse JONES, Chung Kwang Christopher TAN
  • Publication number: 20190027431
    Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.
    Type: Application
    Filed: July 19, 2017
    Publication date: January 24, 2019
    Inventors: Hongxia FENG, Dingying David XU, Sheng C. LI, Matthew L. TINGEY, Meizi JIAO, Chung Kwang Christopher TAN