Abstract: A cleaning composition includes an organic solvent, an organic acid, a chelating agent, a surfactant containing at least one hydroxyl group (OH) at the end, and an ultra pure water, wherein a pH value of the cleaning composition is equal to or higher than 12.

Abstract: A cleaning composition includes an organic solvent, an organic acid, a chelating agent, a surfactant containing at least one hydroxyl group (OH) at the end, and an ultra pure water, wherein a pH value of the cleaning composition is equal to or higher than 12.

Abstract: Method for manufacturing a semiconductor device includes the steps of forming a lower electrode pattern on a substrate, forming a first interlayer insulating layer on the lower electrode pattern, forming an upper electrode pattern on the first interlayer insulating layer, forming a second interlayer insulating layer on the upper electrode pattern, forming an etch blocking layer on a side of the upper electrode pattern, wherein the etch blocking layer passes through the first interlayer insulating layer, forming a cavity which exposes the side of the etch blocking layer by etching the second interlayer insulating layer, and forming a contact ball in the cavity.

Abstract: A method for manufacturing a semiconductor device including at least one of the following steps: (1) Forming a lower electrode pattern on/over a substrate. (2) Forming a first interlayer insulating layer on the lower electrode pattern. (3) Forming an upper electrode pattern on the first interlayer insulating layer. (4) Forming a passivation layer on a side of the upper electrode pattern. (5) Forming a second interlayer insulating layer on the upper electrode pattern. (6) Etching the second interlayer insulating layer to form a cavity which exposes the passivation layer. (7) Forming a contact ball in the cavity.

Abstract: A method for manufacturing a semiconductor device including at least one of the following steps: (1) Forming a lower electrode pattern on/over a substrate. (2) Forming a first interlayer insulating layer on the lower electrode pattern. (3) Forming an upper electrode pattern on the first interlayer insulating layer. (4) Forming a passivation layer on a side of the upper electrode pattern. (5) Forming a second interlayer insulating layer on the upper electrode pattern. (6) Etching the second interlayer insulating layer to form a cavity which exposes the passivation layer. (7) Forming a contact ball in the cavity.

Abstract: Embodiments relate to a method for manufacturing a semiconductor device including at least one of: (1) Forming a lower electrode pattern on/over a substrate. (2) Forming a first interlayer insulating layer on/over the lower electrode pattern. (3) Forming a second interlayer insulating layer over the first interlayer insulating layer to include an intermediate electrode pattern. (4) Forming an upper electrode pattern over the second interlayer insulating layer. (5) Forming a third interlayer insulating layer over the upper electrode pattern. (6) Etching the first to third interlayer insulating layers to form a cavity which exposes a portion of the intermediate electrode pattern. (7) Forming a contact ball in the cavity.

Abstract: Method for manufacturing a semiconductor device includes the steps of forming a lower electrode pattern on a substrate, forming a first interlayer insulating layer on the lower electrode pattern, forming an upper electrode pattern on the first interlayer insulating layer, forming a second interlayer insulating layer on the upper electrode pattern, forming an etch blocking layer on a side of the upper electrode pattern, wherein the etch blocking layer passes through the first interlayer insulating layer, forming a cavity which exposes the side of the etch blocking layer by etching the second interlayer insulating layer, and forming a contact ball in the cavity.

Abstract: A method for manufacturing a backside-illuminated image sensor includes (1) forming an isolation film on the front side of a semiconductor substrate with a buried insulating layer formed therein to define an active region; (2) forming a light-receiving element in the active region of the semiconductor substrate; and (3) forming an inter-layer dielectric layer on the front side of the semiconductor substrate on which the light-receiving element is formed. The method may include forming a super contact hole to pass through the inter-layer dielectric layer and the buried insulating layer in a pad region defined on the front side of the semiconductor substrate reaching the semiconductor substrate. The method may include forming a barrier layer of a metal oxide film containing transition metal at the bottom and sidewall of the super contact hole. The method may include filling a conductive material in the super contact hole, in which the barrier layer is formed, to form a super contact.

Abstract: A semiconductor device and a method for manufacturing the device include connecting a second wafer to a first wafer, forming a hard mask layer on and/or over a backside of the second wafer, forming a hard mask pattern over the second layer and then forming a via hole by etching the first and the second wafers to a predetermined depth using the hard mask pattern as an etching mask.

Abstract: In a method for fabricating a metal interconnection of a semiconductor device, a lower interconnection and a lower insulation layer are formed over a semiconductor substrate. An etch stop layer is formed over the lower insulation layer. An upper insulation layer is formed over the etch stop layer. A first via hole is formed to expose the etch stop layer corresponding to the lower interconnection. A second via hole exposing the lower interconnection is formed by a primary etching process that selectively removes the etch stop layer exposed by the first via hole. A chemical cleaning process is performed on the second via hole, wherein polymer is formed over the surface of the lower interconnection during the chemical cleaning process. The polymer is removed from the second via hole by a secondary etching process using vaporized gas.

Abstract: A method of manufacturing a flash memory device and devices thereof, which may be capable of preventing damage to a gate. A method of manufacturing a flash memory device may include preparing a semiconductor substrate having an active region defined by a device separator. A method of manufacturing a flash memory device may include forming a floating gate, a oxide-nitride-oxide (ONO) layer and/or a control gate layer on and/or over a substrate. A method of manufacturing a flash memory device may include forming a low temperature oxide (LTO) film on and/or over a control gate, etching a LTO film to expose a desired part of a control gate, using a LTO film as a mask to etch a desired part of each of a floating gate layer, a ONO layer and/or a control gate to form a gate pattern, and/or substantially removing a LTO film by wet etching.

Abstract: A method of forming a CMOS image sensor and a CMOS image sensor. A method of forming a CMOS image sensor may include forming a plurality of photodiodes on and/or over a semiconductor substrate at regular intervals, forming an interlayer insulating film on and/or over an entire surface of a semiconductor substrate including photodiodes, coating an organic compound on and/or over an entire surface of an interlayer insulating film, coating photoresist on and/or over an organic compound, subjecting a photoresist to exposure and/or development to form a photoresist pattern which may expose an interlayer insulating film opposite to a photodiode region, selectively etching a portion of an exposed interlayer insulating film using a photoresist pattern as a mask, and/or removing a photoresist pattern.

Abstract: A method for manufacturing a flash memory device is capable of controlling a phenomenon in which a length of the channel between a source and a drain is decreased due to undercut. The method includes forming a gate electrode comprising a floating gate, an ONO film and a control gate using a hard mask pattern over a semiconductor substrate, forming a spacer over the sidewall of the gate electrode, forming an low temperature oxide (LTO) film over the entire surface of the semiconductor substrate including the gate electrode and the spacer, etching the LTO film such that a top portion of the source/drain region and a top portion of the gate electrode are exposed, and removing the LTO film present over the sidewall of the gate electrode by wet-etching.

Abstract: A method for efficiently removing hardened polymer residues generated in the process of forming metal lines. The method includes forming a metal layer over a lower film, forming a sacrificial protective film over the metal layer, forming a photosensitive pattern over the sacrificial protective film, forming a metal line by selectively etching the sacrificial protective film and the metal layer using the photosensitive pattern as a mask such that a residual sacrificial protective film is formed over the metal line, and then removing the residual sacrificial protective film from the metal line.

Abstract: A method of forming a metal line of a semiconductor device, and devices thereof. A method of forming a metal line of a semiconductor device may include forming a multi-layer structure over a substrate, forming a photoresist pattern over a multi-layer structure, forming a metal line by selectively etching a multi-layer structure using a photoresist pattern as an etching mask, removing an electron over a surface of a metal line by processing a surface of a metal line, and/or cleaning a metal line.

Abstract: In a method for fabricating a metal interconnection of a semiconductor device, a lower interconnection and a lower insulation layer are formed over a semiconductor substrate. An etch stop layer is formed over the lower insulation layer. An upper insulation layer is formed over the etch stop layer. A first via hole is formed to expose the etch stop layer corresponding to the lower interconnection. A second via hole exposing the lower interconnection is formed by a primary etching process that selectively removes the etch stop layer exposed by the first via hole. A chemical cleaning process is performed on the second via hole, wherein polymer is formed over the surface of the lower interconnection during the chemical cleaning process. The polymer is removed from the second via hole by a secondary etching process using vaporized gas.

Abstract: A method of manufacturing an image sensor. A method of manufacturing an image sensor may include forming a circuit area including a circuitry on and/or over a semiconductor substrate having a pixel area and/or a peripheral area, provided with a photodiode. A method may include forming a metal interconnection layer, which may include a metal interconnection on and/or over a interlayer dielectric layer, on and/or over a circuit area, forming a trench over a metal interconnection layer of a pixel area, performing a cleaning process on and/or over a the metal interconnection layer including a trench, and/or forming a micro-lens on and/or over a bottom surface of a trench of a metal interconnection layer.

Abstract: Disclosed is a method for fabrication of a CMOS image sensor capable of improving adhesion between an interlayer insulating film and photoresist. According to embodiments in this disclosure, the CMOS image sensor fabrication method may include: forming a plurality of photodiodes over a semiconductor substrate at regular intervals; forming an interlayer insulating film over the semiconductor substrate including the plurality of photodiodes; applying photoresist over the entirety of the interlayer insulating film; hard-baking the photoresist; conducting exposure and development of the photoresist to expose a part of the interlayer insulating film corresponding to the photodiodes, thereby completing a photoresist pattern; and using the photoresist pattern as a mask to selectively etch the exposed part of the interlayer insulating film.

Abstract: A method of manufacturing a flash memory device and devices thereof, which may be capable of preventing damage to a gate. A method of manufacturing a flash memory device may include preparing a semiconductor substrate having an active region defined by a device separator. A method of manufacturing a flash memory device may include forming a floating gate, a oxide-nitride-oxide (ONO) layer and/or a control gate layer on and/or over a substrate. A method of manufacturing a flash memory device may include forming a low temperature oxide (LTO) film on and/or over a control gate, etching a LTO film to expose a desired part of a control gate, using a LTO film as a mask to etch a desired part of each of a floating gate layer, a ONO layer and/or a control gate to form a gate pattern, and/or substantially removing a LTO film by wet etching.

Abstract: A method of forming a CMOS image sensor and a CMOS image sensor. A method of forming a CMOS image sensor may include forming a plurality of photodiodes on and/or over a semiconductor substrate at regular intervals, forming an interlayer insulating film on and/or over an entire surface of a semiconductor substrate including photodiodes, coating an organic compound on and/or over an entire surface of an interlayer insulating film, coating photoresist on and/or over an organic compound, subjecting a photoresist to exposure and/or development to form a photoresist pattern which may expose an interlayer insulating film opposite to a photodiode region, selectively etching a portion of an exposed interlayer insulating film using a photoresist pattern as a mask, and/or removing a photoresist pattern.