Abstract: A network management system and a method of automatic adjustment for a virtualized base station are provided. The method includes following steps. A user equipment (UE) information table is queried from a core network, and a first reserved resource of a first virtualized base station is queried, where the UE information table includes first location information and a first resource requirement corresponding to a first UE set. A second resource requirement corresponding to a second UE set is obtained from the UE information table based on the first location information and a default range. Whether the first reserved resource matches the second resource requirement is determined to generate a determination result. The first reserved resource of the first virtualized base station is expanded or reduced based on the determination result.

Abstract: A display module includes a light-emitting element, a molding layer, a metal contact, an insulating layer, and an array substrate. The light-emitting element has a first surface and a second surface opposite to each other. The light-emitting element has a lead disposed on the first surface. The molding layer laterally surrounds the light-emitting element and has a first surface and a second surface opposite to each other. The first surface of the molding layer is adjacent to the first surface of the light-emitting element. The first surface of the molding layer is a coarse surface. The metal contact covers the lead of the light-emitting element. The insulating layer covers the metal contact and the molding layer. The array substrate is disposed on the insulating layer and having a pad configured to be electrically connected to the metal contact.

Abstract: Disclosed is a microfluidic detection device including a circuit substrate and a transparent substrate. The circuit substrate is provided with at least one first light-emitting device used to emit a detection beam, a photodetector used to receive the detection beam and send out a sensing signal, and a control circuit electrically connected to the first light-emitting device and the photodetector. The transparent substrate overlaps the circuit substrate and is provided with a microfluidic channel and a light guide structure. The light guide structure has a light incident surface disposed corresponding to the first light-emitting device and a light exiting surface disposed corresponding to the photodetector. The light guide structure extends from each of the light incident surface and the light exiting surface to the microfluidic channel and is adapted to transmit the detection beam into and out of the microfluidic channel.

Abstract: A filter device includes one or more filter membranes, and a filter housing enclosing the one or more filter membranes. Each of the filter membranes includes a base membrane made of a ceramic material, and a plurality of through holes. The base membrane is coated with a coating material.

Abstract: A display device includes a substrate, a switching element, a first insulating layer, a first metal layer, and an energy-absorbing layer. The switching element is on the substrate and has a source/drain. The first insulating layer covers the switching element and has a first opening. The first metal layer is on the first insulating layer and extends through the first opening. The energy-absorbing layer is over the first metal layer. A first orthographic projection area of the first opening projected on the substrate is within a second orthographic projection area of the energy-absorbing layer projected on the substrate. A laser reflectivity of a material of the energy-absorbing layer is higher than a laser reflectivity of a material of the source/drain. A laser absorptivity of the material of the energy-absorbing layer is lower than a laser absorptivity of the material of the source/drain.

Abstract: A method for forming an interconnection structure includes depositing a dielectric layer over a first interconnect layer, wherein the first interconnect layer comprises a first metallization layer; forming a via opening in the dielectric layer, and forming a conductive via in the via opening. Forming the via opening includes: etching a recess in the dielectric layer above the first metallization layer; etching a first lateral recess in the dielectric layer at a sidewall of the recess; and after etching the first lateral recess, etching the recess downward to expose the first metallization layer.

Abstract: One aspect of the present disclosure pertains to an integrated (IC) structure. The IC structure includes a semiconductor substrate; an interconnect structure formed over the substrate; and a redistribution layer (RDL) structure formed over the interconnect structure. The RDL structure includes: a RDL pad portion having a pad via array with multiple vias landing on a first top metal line of the interconnect structure; a RDL signal routing portion having a signal routing via landing on a second top metal line of the interconnect structure; and a RDL top portion over the RDL pad portion and the RDL signal routing portion. The multiple vias of the pad via array include a block via and an adjacent sacrificial via, the block via having a block via width, the sacrificial via having a sacrificial via width, and the block via width is greater than the sacrificial via width.

Abstract: A display panel includes a driving circuit layer, light emitting components and encapsulation structures. The light emitting components are disposed on the driving circuit layer, and each includes a first electrode, a light emitting pattern disposed on the first electrode, a second electrode disposed on the light emitting pattern and a pixel definition layer disposed on the driving circuit layer. The pixel definition layer has a pixel opening overlapping with the first electrode. The light emitting pattern and the second electrode cover the pixel definition layer, the first electrode located in the pixel opening and a portion of the driving circuit layer located outside the pixel opening. The encapsulation structures respectively cover the light emitting components, and each encapsulation structure includes a first encapsulation pattern. Edges of the first encapsulation pattern, the light emitting pattern and the second electrode overlapping with each other are aligned with each other.

Abstract: A display element includes a first spacer, a second spacer, at least one first electrode, a second electrode, at least one LED structure, a reflective layer, a first transparent molding layer and a transparent conductive layer. The second spacer is located on one side of the first spacer. The first electrode is surrounded by the first spacer. The second electrode is surrounded by the second spacer. The LED structure is located on the first electrode. The reflective layer is located on a sidewall of the first spacer facing the LED structure. The first transparent molding layer is located on the reflective layer and surrounds the LED structure. The transparent conductive layer is located on the top surface of the second semiconductor layer and the top surface of the first transparent molding layer, and extends to the second electrode.

Abstract: A display panel including a driving circuit layer, multiple light emitting devices and multiple encapsulation structures is provided. The light emitting devices are disposed on the driving circuit layer, and each includes a first electrode, a light emitting pattern, a second electrode and a pixel definition layer. The light emitting pattern is disposed on the first electrode. The second electrode is disposed on the light emitting pattern. The pixel definition layer is disposed on the driving circuit layer, and has a pixel opening overlapping the first electrode. The light emitting pattern and the second electrode cover the pixel definition layer, the first electrode located in the pixel opening of the pixel definition layer and part of the driving circuit layer located outside the pixel opening of the pixel definition layer. The encapsulation structures cover the light emitting devices and each includes a first encapsulation pattern.

Abstract: A switching board and a soldering method thereof are provided. The switching board includes a circuit board having a board body and a first metal ring, where the board body has a first surface, and the first metal ring is formed on the first surface and surrounds a periphery of the board body. The switching board further includes a first metal element disposed on the first surface and fastened to the first metal ring by soldering. The switching board has a high pressure resistance and a low leakage rate.

Abstract: The present invention relates to a method for determining a configuration operable by a configurable electronic device. The device receives a second configuration and a predefined parameter. The device archives a first configuration in the non-transitory computer readable storage medium. The device applies the second configuration and then determine whether the predefined parameter is satisfied. When the predefined parameters are satisfied, the device maintains to apply the second configuration. When the predefined parameter is not satisfied, the device retrieves the first configuration and applies the first configuration.

Abstract: An electronic device includes a temporary storage base, an adhesive layer, light-emitting elements, and a sealant. The adhesive layer is disposed on the temporary storage base. The light-emitting elements are disposed on the adhesive layer. The sealant is disposed on the temporary storage base and surrounds the adhesive layer. In addition, other electronic devices and a manufacturing method of the electronic device are also provided.

Abstract: A laser light source system is used to simultaneously irradiate a plurality of pads on a display substrate and a plurality of light emitting components. The laser light source system includes a laser light source, a collimator lens, a diffractive optical component and a refractive component. The laser light source is configured to provide a laser beam. The collimator lens is disposed on a path of the laser beam to generate a collimated beam. The diffractive optical component is disposed on a path of the collimated beam to generate a plurality of sub beams. The display substrate is disposed on a focal plane of the refractive component, so as to utilize the sub beams to bond the light emitting components to the pads.

Abstract: A fermentation complex with increasing generation of brain dopamine and improving sleeping effect, the fermentation complex containing a vegetable ingredient and use a special polysaccharide fermentation preparation method to get a fermentation complex, within the vegetable ingredient include Gastrodia elata, Black rice, and Wheat seedlings. The fermentation complex has effect of delaying brain aging, protecting brain nerves, calming nerves, and helping to fall asleep.

Abstract: A first and second patterned circuit layer are formed on a first surface and a second surface of a base material. A first adhesive layer is formed on the first patterned circuit layer. A portion of the first surface is exposed by the first patterned circuit layer. The metal reflection layer covers the first insulation layer and a reflectance thereof is greater than or equal to 85%, there is no conductive material between the first patterned circuit layer and the metal reflection layer, and the first adhesive layer is disposed between the first patterned circuit layer and the first insulation layer. A transparent adhesive layer and a protection layer are formed on the metal reflection layer. The transparent adhesive layer is disposed between the metal reflection layer and the protection layer. The protection layer comprises a transparent polymer. The light transmittance is greater than or equal to 80%.

Abstract: An interconnect structure on a semiconductor die includes: a lower conductive layer; an upper conductive layer disposed above the lower conductive layer; and a VIA disposed between the lower conductive layer and the upper conductive layer. The VIA includes: a primary interconnect structure and a sacrificial stress barrier ring disposed around the primary interconnect structure and separated a distance from the primary interconnect structure. A fabrication method for the interconnect structure includes: forming a dielectric layer over a lower conductive layer; patterning photoresist (PR) layer over the dielectric layer to define a location for a plurality of VIA trenches, wherein the patterning includes patterning the PR layer to provide a center opening for the VIA trenches that is surrounded by a ring opening for the VIA trenches, wherein the center opening and the ring opening are spaced apart.

Abstract: A base material is provided. A first patterned circuit layer and a second patterned circuit layer are formed on a first surface and a second surface of the base material. A first insulation layer and a metal reflection layer are provided on the first patterned circuit layer and a portion of the first surface exposed by the first patterned circuit layer, wherein the metal reflection layer covers the first insulation layer, and a reflectance of the metal reflection layer is substantially greater than or equal to 85%, there is no conductive material between the first patterned circuit layer and the metal reflection layer. A first ink layer is formed on the first insulation layer before the metal reflection layer is formed.

Abstract: A method and a device for matching an impedance of pulse radio frequency plasma, and a plasma processing device are provided. In the method, a matched frequency is searched for sequentially in high radio frequency power phases of an i-th pulse period and multiple pulse periods following the i-th pulse period, and a specific modulation frequency determined in a process of searching for the matched frequency in a previous pulse is assigned as an initial frequency for the subsequent pulse. In this way, it is equivalent to increasing a width of a first radio frequency power phase of a pulse period. Therefore, by sequentially performing frequency modulation in the first radio frequency power phases of the multiple pulses, a matched frequency of pulse radio frequency plasma of a high pulse frequency can be found, thereby achieving impedance matching of plasma of a high pulse frequency.

Abstract: Some embodiments relate to a memory device. The memory device includes a magnetoresistive random-access memory (MRAM) cell comprising a magnetic tunnel junction (MTJ). The MTJ device comprises a stack of layers, comprising a bottom electrode disposed over a substrate. A seed layer disposed over the bottom electrode. A buffer layer is disposed between the bottom electrode and the seed layer. The buffer layer prevents diffusion of a diffusive species from the bottom electrode to the seed layer.