Abstract: The present invention, generally speaking, provides for cancellation of non-linear distortions within the echo path of a communications system by characterizing the nonlinearity, performing digital processing of a data signal to cause substantially the same nonlinearity to be applied to the data signal, and inputting a resulting data signal to a non-linear echo-cancellation path. In an exemplary embodiment, the non-linear echo-cancellation path includes as a nonlinear echo canceller a transversal filter or the like. A separate linear echo cancellation path is also provided. Training of the nonlinear echo canceller follows training of the linear echo canceller. This technique is particularly applicable to cancelling the effects of DAC nonlinearity, which can be readily characterized. Using this technique, cancellation improvement of about 3dB can readily be obtained. Alternatively, instead of achieving a lower residual echo floor, the linearity requirements for the transmit DAC can be relaxed.

Abstract: An embodiment of the present invention is related to an analog-to-digital converter comprising a polyphase combiner comprising at least a first combiner filter and a second combiner filter for receiving a plurality of inputs and generating a combined signal. The analog-to-digital converter also comprises a multistage decimator structure for receiving the combined signal and generating a digital sigma-delta output, the multistage decimator structure comprising at least a first decimator comprising a first integrator filter; a first downsampling block and a first differentiator; and a second decimator comprising a second integrator filter; a second downsampling block and a second differentiator.

Abstract: An embodiment of the present invention is related to an analog-to-digital converter comprising a polyphase combiner comprising at least a first combiner filter and a second combiner filter for receiving a plurality of inputs and generating a combined signal. The analog-to-digital converter also comprises a multistage decimator structure for receiving the combined signal and generating a digital sigma-delta output, the multistage decimator structure comprising at least a first decimator comprising a first integrator filter; a first downsampling block and a first differentiator; and a second decimator comprising a second integrator filter; a second downsampling block and a second differentiator.

Abstract: The present invention, generally speaking, provides a digitally-tunable, echo-cancelling analog front end (AFE) for wireline digital communications. The analog front end is especially useful in a High-bit-rate Digital Subscriber Line (HDSL) or HDSL2 environment. An analog echo simulation path is provided capable of simulating echo from a wide variety of echo paths. Digitally controlled attenuators are provided in the transmission path and in the analog echo simulation path. Also provided is a digital-tunable equalizer stage. The equalizer stage is tuned to match the characteristics of the receive path. The same arrangement may be adapted for various DSL technologies, i.e., xDSL. There results an analog front end that is well-adapted to high-speed wireline communications.

Abstract: An IF sampling receiver for use in a wireless communication system includes first and second channels, with one channel generating an in-phase (I) component of an incoming analog IF signal, and the other channel generating a quadrature (Q) component of the analog IF signal. Each of the two channels of the IF sampling receiver includes a corresponding sigma-delta modulator channel. Each of the two sigma-delta modulator channels may be separated into m parallel branches by applying a polyphase decomposition technique to one or more resonators associated with the sigma-delta modulator. The invention thus provides a general framework for configuring a given channel of a sigma-delta modulator to include m parallel branches. The invention also provides a technique for separating a given sigma-delta modulator into n parallel channels, where n is greater than 2. Each of the n parallel channels may then be separated into m parallel branches.