Abstract: Various embodiments of the present disclosure provide a semiconductor device structure. The semiconductor device structure includes a device layer having a first side and a second side opposing the first side, and a first interconnect structure disposed over the first side of the device layer. The first interconnect structure includes a first interconnect-level layer, a second interconnect-level layer disposed over the first interconnect-level layer, wherein the second interconnect-level layer comprises an array of vertical-type memory cell devices. The semiconductor device structure also includes a third interconnect-level layer disposed over the second interconnect-level layer.

Abstract: A semiconductor device includes a first cobalt-containing plug disposed over a substrate, a second cobalt-containing plug disposed over the first cobalt-containing plug, a first barrier layer over sidewalls of the second cobalt-containing plug, a second barrier layer over sidewalls of the first barrier layer, and a dielectric layer surrounding the second barrier layer. The first barrier layer contains a metal element. The first and second barrier layers include different material compositions.

Abstract: A semiconductor fabrication method includes providing a substrate with a logic device formed on the substrate and a plurality of metal routing layers disposed above the logic device and substrate with metal routing connected to the logic device, the plurality of metal routing layers including an upper metal routing layer with metal lines, vias, and a planarized oxide layer; forming a fin structure over the oxide layer in the upper metal routing layer from IGZO; forming a high-K dielectric layer over the oxide layer and the fin structure; forming a storage gate over channel regions of the fin structure; forming a control gate on a first side and a second side of the storage gate; and connecting at least one of the control gate and a source/drain regions of the fin structure to the logic device using VIAs and metal lines.

Abstract: A semiconductor fabrication method includes providing a substrate with a logic device formed on the substrate and a plurality of metal routing layers disposed above the logic device and substrate with metal routing connected to the logic device, the plurality of metal routing layers including an upper metal routing layer with metal lines, vias, and a planarized oxide layer; forming a fin structure over the oxide layer in the upper metal routing layer from IGZO; forming a high-K dielectric layer over the oxide layer and the fin structure; forming a storage gate over channel regions of the fin structure; forming a first control gate on a first side of the storage gate; forming a second control gate on a second side of the storage gate; and connecting the first control gate to a first word line and the second control gate to a second word line.

Abstract: Methods for tuning threshold voltages of fin-like field effect transistor (FinFET) devices are disclosed herein. An exemplary integrated circuit device includes a high voltage n-type FinFET, a high voltage p-type FinFET, a low voltage n-type FinFET, and a low voltage p-type FinFET. Threshold voltages of the high voltage n-type FinFET and the high voltage p-type FinFET are greater than threshold voltages of the low voltage n-type FinFET and the low voltage p-type FinFET, respectively. The high voltage n-type FinFET, the high voltage p-type FinFET, the low voltage n-type FinFET, and the low voltage p-type FinFET each include a threshold voltage tuning layer that includes tantalum and nitrogen. Thicknesses of the threshold voltage tuning layer of the low voltage n-type FinFET and the low voltage p-type FinFET are less than thicknesses of the threshold voltage tuning layer of the high voltage n-type FinFET and the high voltage p-type FinFET, respectively.

Abstract: A thin-film deposition and method deposits thin films on semiconductor wafers. The thin-film deposition utilizes an analysis model that dynamically selects process conditions for a next deposition process by receiving static process conditions and target thin-film data. The analysis model identifies dynamic process conditions data that, together with the static process conditions data, result in predicted thin-film data that matches the target thin-film data. The deposition method then uses the static and dynamic process conditions data for the next thin-film deposition process.

Abstract: A method of forming a semiconductor device includes forming a conductive line over a substrate; forming an etch stop layer (ESL) over the conductive line, the ESL extending continuously along an upper surface of the conductive line and along an upper surface of a first dielectric layer adjacent to the conductive line, where a first lower surface of the ESL contacts the upper surface of the conductive line, and a second lower surface of the ESL contacts the upper surface of the first dielectric layer, the first lower surface being closer to the substrate than the second lower surface; forming a second dielectric layer over the ESL; forming an opening in the second dielectric layer, the opening exposing a first portion of the ESL; removing the first portion of the ESL to expose the conductive line; and filling the opening with an electrically conductive material to form a via.

Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The method includes forming first and second nanostructured channel regions on first and second fin structures, forming first and second oxide layers with first and second thicknesses, forming a dielectric layer with first and second layer portions on the first and second oxide layers, forming first and second capping layers with first and second oxygen diffusivities on the first and second layer portions, growing the first and second oxide layers to have third and fourth thicknesses, and forming a gate metal fill layer over the dielectric layer. The first and second thicknesses are substantially equal to each other and the first and second oxide layers surround the first and second nanostructured channel regions. The second oxygen diffusivity is higher than the first oxygen diffusivity. The fourth thickness is greater than the third thickness.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain epitaxial feature disposed over a substrate, a plurality of semiconductor layers disposed parallelly to each other and in contact with the source/drain epitaxial feature, a gate electrode layer surrounding a portion of each of the plurality of semiconductor layers, and a dielectric region in the substrate below the source/drain epitaxial feature. The dielectric region includes a first oxidation region having a first dopant, and a second oxidation region having a second dopant different than the first dopant.

Abstract: A semiconductor may include an active region, an epitaxial source/drain formed in and extending above the active region, and a first dielectric layer formed over a portion of the active region. The semiconductor may include a first metal gate and a second metal gate formed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer and the second metal gate, and a titanium layer, without an intervening fluorine residual layer, formed on the metal gate and the epitaxial source/drain. The semiconductor may include a first metal layer formed on top of the titanium on the first metal gate, a second metal layer formed on top of the titanium layer on the epitaxial source/drain, and a third dielectric layer formed on the second dielectric layer. The semiconductor may include first and second vias formed in the third dielectric layer.

Abstract: The present teaching relates to method, system, medium, and implementations for region boundary identification and overlay display. An input associated with a 3D object is received. A 3D volumetric model is obtained for the 3D object with multiple regions, each of which includes multiple labeled voxels. A mesh representation is generated for the surface of the 3D object. Region boundaries on surface of the 3D object are identified based on the 3D volumetric model and the mesh representation. The 3D object is rendered, and the region boundaries are overlaid on the rendered 3D object.

Abstract: One aspect of the present disclosure pertains to a memory device. The memory device includes a semiconductor feature made of a compound semiconductor material. The semiconductor features includes a first portion as a first source/drain (S/D) feature, a second portion as a channel, and a third portion as a second S/D feature. The first portion is above the second portion and the second portion is above the third portion, and the second portion vertically extends from the first portion to the third portion. The memory device includes a gate structure horizontally wrapping around the second portion and a capacitor structure in direct contact with and wrapping around the semiconductor feature.

Abstract: A complementary metal oxide semiconductor (CMOS) device includes a transistor of a first type formed over a first substrate, and a transistor of a second type formed over a second substrate. The CMOS device is formed when the transistor of the first type formed on the first substrate is bonded to the transistor of the second type formed over the second substrate.

Abstract: A method of fabricating a semiconductor structure and the semiconductor structure are disclosed. The method uses high flow rate of an etchant and an optimized scan pattern, so that the obtained semiconductor structure is a device upside-down bonded to the carrier wafer without any silicon remaining and is ready for subsequent lithography process for back via contact.

Abstract: Some implementations described herein provide a semiconductor device including a resistor structure. The resistor structure (e.g., a thin film resistor structure) includes a multi-layer film structure connecting contact structures of the resistor structure below the contact structures. The multi-layer film structure includes a capping layer, an upper resistive layer having a first concentration of silicon, and a lower resistive layer having a second concentration of silicon that is lesser relative to the first concentration. The multi-layer film structure may be subject to a lesser risk of oxidation relative to a single layer film structure that does not include the capping layer. Additionally, or alternatively, the combination of the upper and lower resistive layers (e.g., including the first and second concentrations of silicon) may allow for tuning of a mean resistive property and/or a temperature coefficient of resistance across the multi-layer film structure.

Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.

Abstract: The invention relates to an electric bicycle, including a bicycle frame, and one or more control units at least partially accommodated within said bicycle frame. The invention also relates to a control unit for use in such an electric bicycle according to the invention, wherein said control unit is at least partially accommodated within said bicycle frame.

Abstract: A surgical navigation system (100) is provided. The surgical navigation system (100) includes: a head-mounted device (110), which includes a sensor module (111), a processing module (112), and a display module (113); and a plurality of visual markers (120), wherein three-dimensional position and orientation of each visual marker (120) is recognized and tracked by the sensor module (111), and then the processing module (112) calculates spatial conversion relationship between each visual marker (120) to create a local coordinate system, and then the display module (113) generates a virtual image. A method of using the surgical navigation system (100) to assist medical procedure is also provided.

Abstract: A thin-film deposition system deposits a thin-film on a wafer. A radiation source irradiates the wafer with excitation light. An emissions sensor detects an emission spectrum from the wafer responsive to the excitation light. A machine learning based analysis model analyzes the spectrum and detects contamination of the thin-film based on the spectrum.

Abstract: A semiconductor device includes a first transistor formed on a first side of a substrate. The semiconductor device includes a first power rail structure vertically disposed over the first transistor, a second power rail structure vertically disposed over the first power rail structure, and a memory portion vertically disposed over the second power rail structure. The first power rail structure, and a second power rail structure, and the memory portion are all disposed on a second side of the substrate opposite to the first side.