Patents by Inventor Chung-Liang Cheng

Chung-Liang Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12272604
    Abstract: A method of manufacturing a semiconductor device is provided. A substrate is provided. The substrate has a first region and a second region. An n-type work function layer is formed over the substrate in the first region but not in the second region. A p-type work function layer is formed over the n-type work function layer in the first region, and over the substrate in the second region. The p-type work function layer directly contacts the substrate in the second region. And the p-type work function layer includes a metal oxide.
    Type: Grant
    Filed: February 12, 2024
    Date of Patent: April 8, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Liang Cheng, Ziwei Fang
  • Publication number: 20250107149
    Abstract: A deep trench resistor structure and methods of forming the same are described. The structure includes a first trench located in a first dielectric material, a first layer disposed over the first dielectric material, a second layer disposed on the first layer, a second dielectric material disposed over the second layer, and a tunable device in contact with the first layer. The tunable device includes a semiconductor-containing layer in contact with the first layer, a dielectric layer disposed on the semiconductor-containing layer, and a metal-containing layer disposed on the dielectric layer.
    Type: Application
    Filed: March 26, 2024
    Publication date: March 27, 2025
    Inventors: Shih-Yu LIAO, Chung-Liang CHENG
  • Publication number: 20250098241
    Abstract: A semiconductor process system etches gate metals on semiconductor wafers. The semiconductor process system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for an atomic layer etching process. The process system then uses the selected process conditions data for the next etching process.
    Type: Application
    Filed: November 27, 2024
    Publication date: March 20, 2025
    Inventor: Chung-Liang CHENG
  • Publication number: 20250096120
    Abstract: The present disclosure describes a resistor structure with a dielectric layer, trenches, a metal layer, a semiconductor layer, and an insulating layer. The dielectric layer is disposed above electrical components formed on a substrate. The trenches are disposed in the dielectric layer and separated from each other by a dielectric region of the dielectric layer. The metal layer is disposed on a bottom surface and side surfaces of each of the trenches and on a top surface of the dielectric region. The semiconductor layer is disposed on a bottom surface, side surfaces, and a top surface of the metal layer. The insulating layer is disposed in the trenches and in contact with side surfaces of the semiconductor layer and on a top surface of the semiconductor layer.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Yu LIAO, Chung-Liang Cheng
  • Publication number: 20250089229
    Abstract: Various embodiments of the present disclosure are directed to a vertical gate-all-around (GAA) memory cell. A middle conductor overlies a lower conductor and decreases in width towards the lower conductor to culminate in a point spaced from the lower conductor. An insulator structure is between the lower conductor and the middle conductor. A semiconductor channel overlies the middle conductor, and a gate electrode laterally surrounds the semiconductor channel on a sidewall of the semiconductor channel. A gate dielectric layer separates the gate electrode from the semiconductor channel, and an upper conductor overlies the semiconductor channel. The lower and middle conductors and the insulator structure correspond to a resistor, whereas the middle conductor, the upper conductor, the gate electrode, the gate dielectric layer, and the semiconductor channel correspond to a transistor atop the resistor.
    Type: Application
    Filed: January 29, 2024
    Publication date: March 13, 2025
    Inventors: Shih-Yu Liao, Chung-Liang Cheng
  • Patent number: 12250824
    Abstract: A ferroelectric memory cell (FeRAM) is disclosed that includes an active device (e.g., a transistor) and a passive device (e.g., a ferroelectric capacitor) integrated in a substrate. The transistor and its gate contacts are formed on a front side of the substrate. A carrier wafer can be bonded to the active device to allow the active device to be inverted so that the passive device and associated contacts can be electrically coupled from a back side of the substrate.
    Type: Grant
    Filed: November 16, 2023
    Date of Patent: March 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang Cheng, Huang-Lin Chao
  • Publication number: 20250072143
    Abstract: An electrode controls transmittance of a blocking layer over a photodiode of a pixel sensor (e.g., a photodiode of a small pixel detector) by changing oxidation of a metal material included in the blocking layer. By using the electrode to adjust transmittance of the blocking layer, pixel sensors for different uses and/or products may be produced using a single manufacturing process. As a result, power and processing resources are conserved that otherwise would have been expended in switching manufacturing processes. Additionally, production time is decreased (e.g., by eliminating downtime that would otherwise have been used to reconfigure fabrication machines.
    Type: Application
    Filed: November 6, 2024
    Publication date: February 27, 2025
    Inventors: Li-Wen HUANG, Chung-Liang CHENG, Ping-Hao LIN, Kuo-Cheng LEE
  • Patent number: 12237267
    Abstract: A semiconductor device includes a first transistor formed on a first side of a substrate. The semiconductor device includes a first power rail structure vertically disposed over the first transistor, a second power rail structure vertically disposed over the first power rail structure, and a memory portion vertically disposed over the second power rail structure. The first power rail structure, and a second power rail structure, and the memory portion are all disposed on a second side of the substrate opposite to the first side.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Chung-Liang Cheng
  • Publication number: 20250063778
    Abstract: A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.
    Type: Application
    Filed: October 31, 2024
    Publication date: February 20, 2025
    Inventors: Hsin-Yi Lee, Weng Chang, Hsiang-Pi Chang, Huang-Lin Chao, Chung-Liang Cheng, Chi On Chui, Kun-Yu Lee, Tzer-Min Shen, Yen-Tien Tung, Chun-I Wu
  • Patent number: 12230503
    Abstract: A semiconductor process system etches gate metals on semiconductor wafers. The semiconductor process system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for an etching process. The process system then uses the selected process conditions data for the next etching process.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: February 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chung-Liang Cheng
  • Publication number: 20250048644
    Abstract: The present disclosure describes a structure with a substrate, a first interconnect region, a second interconnect region, and a memory device region. The first interconnect region is over the substrate and includes first interconnect structures. The second interconnect region is over the first interconnect region and includes second interconnect structures electrically connected to the first interconnect structures. Further, the memory device region is between the first and second interconnect regions and includes memory cells (e.g., ferroelectric random access memory (FeRAM) cells).
    Type: Application
    Filed: February 20, 2024
    Publication date: February 6, 2025
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Yu LIAO, Chung-Liang Cheng
  • Publication number: 20250046677
    Abstract: A semiconductor structure and method for forming the semiconductor are provided. The semiconductor structure includes a logic device, a first contact connected to the logic device, a first power rail over the logic device and connected to the logic device, and a second power rail over the logic device. A transistor having a channel region including indium, gallium, zinc, and oxygen is over the second power rail and connected to the second power rail.
    Type: Application
    Filed: July 31, 2023
    Publication date: February 6, 2025
    Inventors: Shih-Yu LIAO, Chung-Liang Cheng
  • Publication number: 20250038049
    Abstract: A method of forming a semiconductor structure includes forming a conductive capping layer over a conductive feature, forming a dielectric layer over the conductive capping layer, forming an opening in the dielectric layer to expose a top surface of the conductive capping layer, forming an inhibitor film at the top surface of the conductive capping layer, depositing a barrier layer on sidewalls of the opening, removing the inhibitor film to expose the top surface of the conductive capping layer, depositing a supplementary liner on the barrier layer and the top surface of the conductive capping layer, and depositing a conductive material on the supplementary liner and filling the opening.
    Type: Application
    Filed: July 25, 2023
    Publication date: January 30, 2025
    Inventors: Yen Yu Chen, Chung-Liang Cheng, Ying-Han Chiou
  • Patent number: 12213323
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Liang Liu, Sheng-Chau Chen, Chung-Liang Cheng, Chia-Shiung Tsai, Yeong-Jyh Lin, Pinyen Lin, Huang-Lin Chao
  • Patent number: 12205850
    Abstract: A semiconductor device includes a first gate structure that includes a first interfacial layer, a first gate dielectric layer disposed over the first interfacial layer, and a first gate electrode disposed over the first gate dielectric layer. The semiconductor device also includes a second gate structure that includes a second interfacial layer, a second gate dielectric layer disposed over the second interfacial layer, and a second gate electrode disposed over the second gate dielectric layer. The first interfacial layer contains a different amount of a dipole material than the second interfacial layer.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Yen-Yu Chen, Chung-Liang Cheng
  • Patent number: 12205997
    Abstract: An integrated circuit includes a first chip bonded to a second chip. The first chip includes gate all around transistors on a substrate. The first chip includes backside conductive vias extending through the substrate to the gate all around transistors. The second chip includes electronic circuitry electrically connected to the transistors by the backside conductive vias.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: January 21, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chung-Liang Cheng
  • Publication number: 20250016983
    Abstract: Memory cells, semiconductor devices, semiconductor stacked structures, and fabrication methods are provided. An example memory cell includes a capacitor and a transistor stacked over the capacitor in a compact configuration. The capacitor includes a floating gate, a high-k dielectric layer, and a metal gate. The metal gate extends horizontally from a first sidewall to a second sidewall and vertically from a bottom surface to a top surface. The transistor includes the metal gate and a gate dielectric layer disposed on the metal gate. The gate dielectric layer includes two side portions respectively disposed on the two sidewalls of the metal gate and, and a top portion disposed on the top surface of the metal gate. The transistor further includes two separate S/D regions respectively formed on the two side portions of the gate dielectric layer, and a channel region formed on the top portion of the gate dielectric layer.
    Type: Application
    Filed: July 5, 2023
    Publication date: January 9, 2025
    Inventors: Shih-Yu Liao, Chung-Liang Cheng
  • Publication number: 20250008244
    Abstract: A stacked CMOS image sensor (CIS) structure is provided. The stacked CIS structure comprises a first die, a second die and a third die. The first die comprises a photodiode, a transfer gate, a selective conversion gain (SCG) switch, a reset switch, a floating node diffusion capacitor and a SCG diffusion capacitor. The second die comprises a source follower transistor and a row select switch. The third die comprises an image sensing circuit electrically connected to the third floating node.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 2, 2025
    Inventors: MING-HSIEN YANG, CHIA-YU WEI, CHUN-HAO CHOU, KUO-CHENG LEE, CHUNG-LIANG CHENG, SHENG-CHAU CHEN
  • Patent number: 12183787
    Abstract: A semiconductor process system etches gate metals on semiconductor wafers. The semiconductor process system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for an atomic layer etching process. The process system then uses the selected process conditions data for the next etching process.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: December 31, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chung-Liang Cheng
  • Patent number: 12176392
    Abstract: A semiconductor process system etches gate metals on semiconductor wafers. The semiconductor process system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for an atomic layer etching process. The process system then uses the selected process conditions data for the next etching process.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: December 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chung-Liang Cheng