Patents by Inventor Chung-Liang Cheng

Chung-Liang Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11322410
    Abstract: Methods for tuning threshold voltages of fin-like field effect transistor (FinFET) devices are disclosed herein. An exemplary integrated circuit device includes a high voltage n-type FinFET, a high voltage p-type FinFET, a low voltage n-type FinFET, and a low voltage p-type FinFET. Threshold voltages of the high voltage n-type FinFET and the high voltage p-type FinFET are greater than threshold voltages of the low voltage n-type FinFET and the low voltage p-type FinFET, respectively. The high voltage n-type FinFET, the high voltage p-type FinFET, the low voltage n-type FinFET, and the low voltage p-type FinFET each include a threshold voltage tuning layer that includes tantalum and nitrogen. Thicknesses of the threshold voltage tuning layer of the low voltage n-type FinFET and the low voltage p-type FinFET are less than thicknesses of the threshold voltage tuning layer of the high voltage n-type FinFET and the high voltage p-type FinFET, respectively.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: May 3, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Liang Cheng, Wei-Jen Chen, Yen-Yu Chen, Ming-Hsien Lin
  • Patent number: 11295989
    Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes first and second gate structures disposed on first and second nanostructured channel regions, respectively. The first gate structure includes a nWFM layer disposed on the first nanostructured channel region, a barrier layer disposed on the nWFM layer, a first pWFM layer disposed on the barrier layer, and a first gate fill layer disposed on the first pWFM layer. Sidewalls of the first gate fill layer are in physical contact with the barrier layer. The second gate structure includes a gate dielectric layer disposed on the second nanostructured channel region, a second pWFM layer disposed on the gate dielectric layer, and a second gate fill layer disposed on the pWFM layer. Sidewalls of the second gate fill layer are in physical contact with the gate dielectric layer.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: April 5, 2022
    Inventor: Chung-Liang Cheng
  • Publication number: 20220102218
    Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The method includes forming first and second nanostructured channel regions on first and second fin structures, forming first and second oxide layers with first and second thicknesses, forming a dielectric layer with first and second layer portions on the first and second oxide layers, forming first and second capping layers with first and second oxygen diffusivities on the first and second layer portions, growing the first and second oxide layers to have third and fourth thicknesses, and forming a gate metal fill layer over the dielectric layer. The first and second thicknesses are substantially equal to each other and the first and second oxide layers surround the first and second nanostructured channel regions. The second oxygen diffusivity is higher than the first oxygen diffusivity. The fourth thickness is greater than the third thickness.
    Type: Application
    Filed: March 10, 2021
    Publication date: March 31, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chung-Liang CHENG
  • Publication number: 20220077296
    Abstract: The embodiments described herein are directed to a method for the fabrication of transistors with aluminum-free n-type work function layers as opposed to aluminum-based n-type work function layers. The method includes forming a channel portion disposed between spaced apart source/drain epitaxial layers and forming a gate stack on the channel portion, where forming the gate stack includes depositing a high-k dielectric layer on the channel portion and depositing a p-type work function layer on the dielectric layer. After depositing the p-type work function layer, forming without a vacuum break, an aluminum-free n-type work function layer on the p-type work function layer and depositing a metal on the aluminum-free n-type work function layer. The method further includes depositing an insulating layer to surround the spaced apart source/drain epitaxial layers and the gate stack.
    Type: Application
    Filed: November 22, 2021
    Publication date: March 10, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Liang CHENG, Ziwei FANG, Chun-I WU, Huang-Lin CHAO
  • Patent number: 11264503
    Abstract: A method of fabricating a semiconductor device includes forming first and second nanostructured layers arranged in an alternating configuration on a substrate, forming first and second nanostructured channel regions in the first nanostructured layers, forming first and second gate-all-around structures wrapped around each of the first and second nanostructured channel regions. The forming the GAA structures includes depositing first and second gate barrier layers having similar material compositions and work function values on the first and second gate dielectric layers, forming first and second diffusion barrier layers on the first and second gate barrier layers, and doping the first and second gate barrier layers from a dopant source layer through the first and second diffusion barrier layers. The first diffusion barrier layer is thicker than the second diffusion barrier layer and the doped first and second gate barrier layers have work function values and doping concentrations different from each other.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang Cheng, Ziwei Fang
  • Patent number: 11257755
    Abstract: The present disclosure describes a method for forming a barrier structure between liner-free conductive structures and underlying conductive structures. The method includes forming openings in a dielectric layer disposed on a contact layer, where the openings expose conductive structures in the contact layer. A first metal layer is deposited in the openings and is grown thicker on top surfaces of the conductive structures and thinner on sidewall surfaces of the openings. The method further includes exposing the first metal layer to ammonia to form a bilayer with the first metal layer and a nitride of the first metal layer, and subsequently exposing the nitride to an oxygen plasma to convert a portion of the nitride of the first metal layer to an oxide layer. The method also includes removing the oxide layer and forming a semiconductor-containing layer on the nitride of the first metal layer.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: February 22, 2022
    Inventors: Yen-Yu Chen, Chung-Liang Cheng
  • Publication number: 20220052258
    Abstract: A resistive random access memory cell includes a gate all around transistor and a resistor device. The resistor device includes a first electrode including a plurality of conductive nanosheets. The resistor device includes a high-K resistive element surrounds the conductive nanosheets. The resistor device includes a second electrode separated from the conductive nanosheets by the resistive element.
    Type: Application
    Filed: March 5, 2021
    Publication date: February 17, 2022
    Inventor: Chung-Liang CHENG
  • Patent number: 11251078
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first conductive feature over a semiconductor substrate. The method includes forming an oxygen-absorbing layer on a surface of the first conductive feature. The oxygen-absorbing layer absorbs oxygen from the first conductive feature and becomes an oxygen-containing layer. The method includes removing the oxygen-containing layer to expose the surface originally covered by the oxygen-containing layer. The method includes forming a metal-containing layer on the surface. The method includes forming a second conductive feature on the metal-containing layer.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: February 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang Cheng, Ziwei Fang
  • Publication number: 20220037510
    Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the fin structure adjacent to the S/D region. The gate structure includes a gate stack disposed on the fin structure and a gate capping structure disposed on the gate stack. The gate capping structure includes a conductive gate cap disposed on the gate stack and an insulating gate cap disposed on the conductive gate cap. The semiconductor device further includes a first contact structure disposed over the gate stack. A portion of the first contact structure is disposed within the gate capping structure and is separated from the gate stack by a portion of the conductive gate cap.
    Type: Application
    Filed: April 29, 2021
    Publication date: February 3, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chung-Liang CHENG
  • Publication number: 20220013523
    Abstract: A device includes a substrate. A first nanostructure is over the substrate, and includes a semiconductor having a first resistance. A second nanostructure is over the substrate, is offset laterally from the first nanostructure, is at about the same height above the substrate as the first nanostructure, and includes a conductor having a second resistance lower than the first resistance. A first gate structure is over and wrapped around the first nanostructure, and a second gate structure is over and wrapped around the second nanostructure.
    Type: Application
    Filed: March 9, 2021
    Publication date: January 13, 2022
    Inventor: Chung-Liang CHENG
  • Publication number: 20210407814
    Abstract: A semiconductor process system etches gate metals on semiconductor wafers. The semiconductor process system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for an etching process. The process system then uses the selected process conditions data for the next etching process.
    Type: Application
    Filed: March 4, 2021
    Publication date: December 30, 2021
    Inventor: Chung-Liang CHENG
  • Publication number: 20210408259
    Abstract: A device includes a substrate, a semiconductor channel over the substrate, and a gate structure over and laterally surrounding the semiconductor channel. The gate structure includes a first dielectric layer over the semiconductor channel, a first work function metal layer over the first dielectric layer, a first protection layer over the first work function metal layer, a second protection layer over the first protection layer, and a metal fill layer over the second protection layer.
    Type: Application
    Filed: March 8, 2021
    Publication date: December 30, 2021
    Inventor: Chung-Liang CHENG
  • Publication number: 20210408235
    Abstract: A semiconductor process system etches gate metals on semiconductor wafers. The semiconductor process system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for an atomic layer etching process. The process system then uses the selected process conditions data for the next etching process.
    Type: Application
    Filed: March 5, 2021
    Publication date: December 30, 2021
    Inventor: Chung-Liang CHENG
  • Publication number: 20210398900
    Abstract: A semiconductor process system etches thin films on semiconductor wafers. The semiconductor process system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for an etching process by receiving static process conditions and target thin-film data. The analysis model identifies dynamic process conditions data that, together with the static process conditions data, result in predicted remaining thin-film data that matches the target thin-film data. The process system then uses the static and dynamic process conditions data for the next etching process.
    Type: Application
    Filed: March 5, 2021
    Publication date: December 23, 2021
    Inventor: Chung-Liang CHENG
  • Publication number: 20210399107
    Abstract: A semiconductor structure is provided. The semiconductor structure includes nanostructures stacked over a substrate and spaced apart from one another, gate dielectric layers wrapping around the nanostructures respectively, nitride layers wrapping around the gate dielectric layers respectively, oxide layers wrapping around the nitride layers respectively, work function layers wrapping around the oxide layers respectively, and a metal fill layer continuously surrounding the work function layers.
    Type: Application
    Filed: August 30, 2021
    Publication date: December 23, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Liang CHENG, Ziwei FANG
  • Publication number: 20210391255
    Abstract: The present disclosure describes a method for forming a barrier structure between liner-free conductive structures and underlying conductive structures. The method includes forming openings in a dielectric layer disposed on a contact layer, where the openings expose conductive structures in the contact layer. A first metal layer is deposited in the openings and is grown thicker on top surfaces of the conductive structures and thinner on sidewall surfaces of the openings. The method further includes exposing the first metal layer to ammonia to form a bilayer with the first metal layer and a nitride of the first metal layer, and subsequently exposing the nitride to an oxygen plasma to convert a portion of the nitride of the first metal layer to an oxide layer. The method also includes removing the oxide layer and forming a semiconductor-containing layer on the nitride of the first metal layer.
    Type: Application
    Filed: June 15, 2020
    Publication date: December 16, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen -Yu CHEN, Chung-Liang CHENG
  • Publication number: 20210384313
    Abstract: A device comprises a substrate, a semiconductor channel over the substrate, and a gate structure over and laterally surrounding the semiconductor channel. The gate structure comprises a first dielectric layer comprising a first dielectric material including dopants. A second dielectric layer is on the first dielectric layer, and comprises a second dielectric material substantially free of the dopants. A metal fill layer is over the second dielectric layer.
    Type: Application
    Filed: March 3, 2021
    Publication date: December 9, 2021
    Inventor: Chung-Liang Cheng
  • Publication number: 20210375698
    Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes first and second gate structures disposed on first and second nanostructured channel regions, respectively. The first gate structure includes a nWFM layer disposed on the first nanostructured channel region, a barrier layer disposed on the nWFM layer, a first pWFM layer disposed on the barrier layer, and a first gate fill layer disposed on the first pWFM layer. Sidewalls of the first gate fill layer are in physical contact with the barrier layer. The second gate structure includes a gate dielectric layer disposed on the second nanostructured channel region, a second pWFM layer disposed on the gate dielectric layer, and a second gate fill layer disposed on the pWFM layer. Sidewalls of the second gate fill layer are in physical contact with the gate dielectric layer.
    Type: Application
    Filed: September 28, 2020
    Publication date: December 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chung-Liang CHENG
  • Publication number: 20210366785
    Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes first and second nanostructured channel regions in first and second nanostructured layers, respectively, and first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The first GAA structure includes an Al-based gate stack with a first gate dielectric layer, an Al-based n-type work function metal layer, a first metal capping layer, and a first gate metal fill layer. The second GAA structure includes an Al-free gate stack with a second gate dielectric layer, an Al-free p-type work function metal layer, a metal growth inhibition layer, a second metal capping layer, and a second gate metal fill layer.
    Type: Application
    Filed: August 9, 2021
    Publication date: November 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang Cheng, Ziwei FANG
  • Publication number: 20210367032
    Abstract: The present disclosure is directed to gate-all-around (GAA) transistor structures with a low level of leakage current and low power consumption. For example, the GAA transistor includes a semiconductor layer with a first source/drain (S/D) epitaxial structure and a second S/D epitaxial structure disposed thereon, where the first and second S/D epitaxial structures are spaced apart by semiconductor nano-sheet layers. The semiconductor structure further includes isolation structures interposed between the semiconductor layer and each of the first and second S/D epitaxial structures. The GAA transistor further includes a gate stack surrounding the semiconductor nano-sheet layers.
    Type: Application
    Filed: May 19, 2020
    Publication date: November 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Yu CHEN, Chung-Liang CHENG