Abstract: A semiconductor device includes an active region over a substrate; a first cobalt-containing feature disposed over the active region; a conductive cap disposed over and in physical contact with the first cobalt-containing feature; and a second cobalt-containing feature disposed over and in physical contact with the conductive cap.

Abstract: Examples of a method of forming an integrated circuit device with an interfacial layer disposed between a channel region and a gate dielectric are provided herein. In some examples, the method includes receiving a workpiece having a substrate and a fin having a channel region disposed on the substrate. An interfacial layer is formed on the channel region of the fin, and a gate dielectric layer is formed on the interfacial layer. A first capping layer is formed on the gate dielectric layer, and a second capping layer is formed on the first capping layer. An annealing process is performed on the workpiece configured to cause a first material to diffuse from the first capping layer into the gate dielectric layer. The forming of the first and second capping layers and the annealing process may be performed in the same chamber of a fabrication tool.

Abstract: A semiconductor device and a method of forming the same are provided. In one embodiment, the semiconductor device includes a semiconductor substrate, a plurality of channel regions including first, second, and third p-type channel regions as well as first, second, and third n-type channel regions, and a plurality of gate structures. The plurality of gate structures includes an interfacial layer (IL) disposed over the plurality of channel regions, a first high-k (HK) dielectric layer disposed over the first p-type channel region and the first n-type channel region, a second high-k dielectric layer disposed over the first n-type channel region, the second n-type channel region, the first p-type channel region, and the second p-type channel region; and a third high-k dielectric layer disposed over the plurality of channel regions. The first, second and third high-k dielectric layers are different from one another.

Abstract: Examples of an integrated circuit with a gate structure and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate having a channel region. A gate dielectric is formed on the channel region, and a layer containing a dopant is formed on the gate dielectric. The workpiece is annealed to transfer the dopant to the gate dielectric, and the layer is removed after the annealing. In some such examples, after the layer is removed, a work function layer is formed on the gate dielectric and a fill material is formed on the work function layer to form a gate structure.

Abstract: A method for forming a gate structure includes forming a trench within an interlayer dielectric layer (ILD) that is disposed on a semiconductor substrate, the trench exposing a top surface of the semiconductor substrate, forming an interfacial layer at a bottom of the trench, forming a dielectric layer within the trench, forming a work function metal layer on the dielectric layer, forming an in-situ nitride layer on the work function metal layer in the trench, performing a first cobalt deposition process to form a cobalt layer within the trench, performing a second cobalt deposition process to increase a thickness of the cobalt layer within the trench, and performing an electrochemical plating (ECP) process to fill the trench with cobalt.

Abstract: A first conductive feature has a dielectric layer formed thereover. An opening is formed in the dielectric layer to expose a portion of the first conductive feature. A first barrier layer is formed over the first conductive feature and over a top surface of the dielectric layer. A second barrier layer is formed over the first barrier layer and on sidewalls of the opening. The second barrier layer is removed, resulting in at least a portion of the first barrier layer disposed over the first conductive feature. A second conductive feature is formed over the portion of the first barrier layer. Sidewalls of the second conductive feature directly contact the dielectric layer.

Abstract: A semiconductor device includes: a fin structure disposed on a substrate; a gate feature that traverses the fin structure to overlay a central portion of the fin structure; a pair of source/drain features, along the fin structure, that are disposed at respective sides of the gate feature; and a plurality of contact structures that are formed of tungsten, wherein a gate electrode of the gate feature and the pair of source/drain features are each directly coupled to a respective one of the plurality of contact structures.

Abstract: A structure and a formation method of a semiconductor device structure are provided. The method includes forming a first fin structure, a second fin structure, and a third fin structure over a semiconductor substrate. The method includes forming first spacer elements over sidewalls of the first fin structure and the second fin structure and partially removing the first fin structure and the second fin structure. The method includes forming second spacer elements over sidewalls of the third fin structure and partially removing the third fin structure. The second spacer element is taller than the first spacer element. The method includes epitaxially growing a semiconductor material over the first fin structure, the second fin structure, and the third fin structure such that a merged semiconductor element is formed on the first fin structure and the second fin structure, and a semiconductor element is formed on the third fin structure.

Abstract: A structure and a formation method of a semiconductor device structure are provided. The method includes forming a first fin structure, a second fin structure, and a third fin structure over a semiconductor substrate. The method includes forming first spacer elements over sidewalls of the first fin structure and the second fin structure and partially removing the first fin structure and the second fin structure. The method includes forming second spacer elements over sidewalls of the third fin structure and partially removing the third fin structure. The second spacer element is taller than the first spacer element. The method includes epitaxially growing a semiconductor material over the first fin structure, the second fin structure, and the third fin structure such that a merged semiconductor element is formed on the first fin structure and the second fin structure, and a semiconductor element is formed on the third fin structure.

Abstract: Examples of an integrated circuit with a gate structure and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate having a channel region. A gate dielectric is formed on the channel region, and a layer containing a dopant is formed on the gate dielectric. The workpiece is annealed to transfer the dopant to the gate dielectric, and the layer is removed after the annealing. In some such examples, after the layer is removed, a work function layer is formed on the gate dielectric and a fill material is formed on the work function layer to form a gate structure.

Abstract: A semiconductor device includes an active region over a substrate; a first cobalt-containing feature disposed over the active region; a conductive cap disposed over and in physical contact with the first cobalt-containing feature; and a second cobalt-containing feature disposed over and in physical contact with the conductive cap.

Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary method includes forming a contact opening in a dielectric layer. The contact opening has sidewalls defined by the dielectric layer and a bottom defined by a conductive feature. An ALD-like nitrogen-containing plasma pre-treatment process is performed on the sidewalls (and, in some implementations, the bottom) of the contact opening. An ALD process is performed to form a titanium-and-nitrogen containing barrier layer over the sidewalls and the bottom of the contact opening. A cobalt-containing bulk layer is then formed over the titanium-and-nitrogen-containing barrier layer. A cycle of the ALD-like nitrogen-containing plasma pre-treatment process can include a nitrogen-containing plasma pulse phase and a purge phase. A cycle of the ALD process can include a titanium-containing pulse phase, a first purge phase, a nitrogen-containing plasma pulse phase, and a second purge phase.

Abstract: Methods for tuning threshold voltages of fin-like field effect transistor devices are disclosed herein. An exemplary method includes forming a first opening in a first gate structure and a second opening in a second gate structure. The first gate structure is disposed over a first fin structure, and the second gate structure is disposed over a second fin structure. The method further includes filling the first opening and the second opening by forming a gate dielectric layer, forming a threshold voltage tuning layer over the gate dielectric layer, etching back the threshold voltage tuning layer in the second opening, forming a work function layer over the threshold voltage tuning layer, and forming a metal fill layer over the work function layer. The threshold voltage tuning layer includes tantalum and nitrogen. The etching back uses a tungsten-chloride containing precursor.

Abstract: Examples of an integrated circuit with a gate structure and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate having a channel region. A gate dielectric is formed on the channel region, and a layer containing a dopant is formed on the gate dielectric. The workpiece is annealed to transfer the dopant to the gate dielectric, and the layer is removed after the annealing. In some such examples, after the layer is removed, a work function layer is formed on the gate dielectric and a fill material is formed on the work function layer to form a gate structure.

Abstract: Methods for tuning threshold voltages of fin-like field effect transistor (FinFET) devices are disclosed herein. An exemplary integrated circuit device includes a high voltage n-type FinFET, a high voltage p-type FinFET, a low voltage n-type FinFET, and a low voltage p-type FinFET. Threshold voltages of the high voltage n-type FinFET and the high voltage p-type FinFET are greater than threshold voltages of the low voltage n-type FinFET and the low voltage p-type FinFET, respectively. The high voltage n-type FinFET, the high voltage p-type FinFET, the low voltage n-type FinFET, and the low voltage p-type FinFET each include a threshold voltage tuning layer that includes tantalum and nitrogen. Thicknesses of the threshold voltage tuning layer of the low voltage n-type FinFET and the low voltage p-type FinFET are less than thicknesses of the threshold voltage tuning layer of the high voltage n-type FinFET and the high voltage p-type FinFET, respectively.

Abstract: A semiconductor device includes: a fin structure disposed on a substrate; a gate feature that traverses the fin structure to overlay a central portion of the fin structure; a pair of source/drain features, along the fin structure, that are disposed at respective sides of the gate feature; and a plurality of contact structures that are formed of tungsten, wherein a gate electrode of the gate feature and the pair of source/drain features are each directly coupled to a respective one of the plurality of contact structures.

Abstract: A chemical-mechanical planarization (CMP) system includes a platen, a pad, a polish head, a rotating mechanism, a light source, and a detector. The pad is disposed on the platen. The polish head is configured to hold a wafer against the pad. The rotating mechanism is configured to rotate at least one of the platen and the polish head. The light source is configured to provide incident light to an end-point layer on the wafer. The detector is configured to detect absorption of the incident light by the end-point layer.

Abstract: A semiconductor device includes: a first conductive structure having sidewalls and a bottom surface, the first conductive structure extending through one or more isolation layers formed on a substrate; and an insulation layer disposed between at least one of the sidewalls of the first conductive structure and respective sidewalls of the one or more isolation layers, wherein the first conductive structure is electrically coupled to a second conductive structure through at least the bottom surface.

Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary method includes forming a contact opening in a dielectric layer. The contact opening has sidewalls defined by the dielectric layer and a bottom defined by a conductive feature. An ALD-like nitrogen-containing plasma pre-treatment process is performed on the sidewalls (and, in some implementations, the bottom) of the contact opening. An ALD process is performed to form a titanium-and-nitrogen containing barrier layer over the sidewalls and the bottom of the contact opening. A cobalt-containing bulk layer is then formed over the titanium-and-nitrogen-containing barrier layer. A cycle of the ALD-like nitrogen-containing plasma pre-treatment process can include a nitrogen-containing plasma pulse phase and a purge phase. A cycle of the ALD process can include a titanium-containing pulse phase, a first purge phase, a nitrogen-containing plasma pulse phase, and a second purge phase.

Abstract: A chemical-mechanical planarization (CMP) system includes a platen, a pad, a polish head, a rotating mechanism, a light source, and a detector. The pad is disposed on the platen. The polish head is configured to hold a wafer against the pad. The rotating mechanism is configured to rotate at least one of the platen and the polish head. The light source is configured to provide incident light to an end-point layer on the wafer. The detector is configured to detect absorption of the incident light by the end-point layer.