Patents by Inventor Chung-Liang TSAI

Chung-Liang TSAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145561
    Abstract: A semiconductor may include an active region, an epitaxial source/drain formed in and extending above the active region, and a first dielectric layer formed over a portion of the active region. The semiconductor may include a first metal gate and a second metal gate formed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer and the second metal gate, and a titanium layer, without an intervening fluorine residual layer, formed on the metal gate and the epitaxial source/drain. The semiconductor may include a first metal layer formed on top of the titanium on the first metal gate, a second metal layer formed on top of the titanium layer on the epitaxial source/drain, and a third dielectric layer formed on the second dielectric layer. The semiconductor may include first and second vias formed in the third dielectric layer.
    Type: Application
    Filed: January 10, 2024
    Publication date: May 2, 2024
    Inventors: Yu-Ting TSAI, Chung-Liang CHENG, Hong-Ming LO, Chun-Chih LIN, Chyi-Tsong NI
  • Patent number: 11935804
    Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Ming Hung Tseng, Yen-Liang Lin, Hao-Yi Tsai, Chi-Ming Tsai, Chung-Shi Liu, Chih-Wei Lin, Ming-Che Ho
  • Publication number: 20240084455
    Abstract: Some implementations described herein include systems and techniques for fabricating a wafer-on-wafer product using a filled lateral gap between beveled regions of wafers included in a stacked-wafer assembly and along a perimeter region of the stacked-wafer assembly. The systems and techniques include a deposition tool having an electrode with a protrusion that enhances an electromagnetic field along the perimeter region of the stacked-wafer assembly during a deposition operation performed by the deposition tool. Relative to an electromagnetic field generated by a deposition tool not including the electrode with the protrusion, the enhanced electromagnetic field improves the deposition operation so that a supporting fill material may be sufficiently deposited.
    Type: Application
    Filed: February 8, 2023
    Publication date: March 14, 2024
    Inventors: Che Wei YANG, Chih Cheng SHIH, Kuo Liang LU, Yu JIANG, Sheng-Chan LI, Kuo-Ming WU, Sheng-Chau CHEN, Chung-Yi YU, Cheng-Yuan TSAI
  • Patent number: 11925033
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Liang Liu, Sheng-Chau Chen, Chung-Liang Cheng, Chia-Shiung Tsai, Yeong-Jyh Lin, Pinyen Lin, Huang-Lin Chao
  • Patent number: 11917772
    Abstract: A power supply with a separable communication module includes a casing with a port; a main board placed in the casing and having a power conversion circuit; a sub-board electrically connected to the power conversion circuit and provided with at least one first connector; and a communication module. The power conversion circuit has at least one electrical connection terminal. A first interface of the first connector faces the port. The communication module includes a first circuit board and a communication circuit disposed on the first circuit board, the first circuit board has an electrical connection part electrically connected to the communication circuit, the electrical connection part has a first state of connecting with the first interface, and a second state of detaching from the first interface.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: February 27, 2024
    Assignee: COTEK ELECTRONIC IND. CO., LTD.
    Inventors: Chun-Wei Wu, Ta-Chang Wei, Chung-Liang Tsai, Shou-Cheng Yeh
  • Publication number: 20230180401
    Abstract: A power supply comprises a casing with a port; a main board placed in the casing and having a power conversion circuit; a sub-board electrically connected to the power conversion circuit and provided with at least one first connector; and a communication module. The power conversion circuit has at least one electrical connection terminal. A first interface of the first connector faces the port. The communication module comprises a first circuit board and a communication circuit disposed on the first circuit board, the first circuit board has an electrical connection part electrically connected to the communication circuit, the electrical connection part has a first state of connecting with the first interface so that the communication module and the power conversion circuit are electrically connected, and a second state of detaching from the first interface so that the communication module is separated from and electrically disconnected with the sub-board.
    Type: Application
    Filed: December 6, 2021
    Publication date: June 8, 2023
    Inventors: Chun-Wei WU, Ta-Chang WEI, Chung-Liang TSAI, Shou-Cheng YEH