Abstract: An antenna-in-package construction includes a chip layer, a second dielectric layer, and a first dielectric layer stacked in order. The first dielectric layer has a dielectric constant more than 3.5. The antenna-in-package construction includes a transmitting antenna array, a receiving antenna array, and metal isolated pillars. The transmitting antenna array extends from the chip layer to the first dielectric layer through the second dielectric layer. The receiving antenna array extends from the chip layer to the second dielectric layer. The transmitting antenna array and the receiving antenna array are arranged in an alternating interleaved sequence. The metal isolated pillars surround each transmitting antenna and each receiving antenna. The chip layer includes at least one transmitting chip and at least one receiving chip. The transmitting chip and the receiving chip are electrically connected to the transmitting antenna array and the receiving antenna array, respectively.

Abstract: Methods, systems, and apparatuses include determining to apply a read retry operation to a portion of memory. The likelihood of a read retry timeout meeting a threshold is determined. A reverse trim setting is selected in response to determining the likelihood of the read retry timeout meets the threshold. The read retry operation is executed using the selected trim setting.

Abstract: In some implementations, a memory device may receive a program command. The memory device may determine whether a portion of the memory is associated with a reliability risk. The memory device may determine, based on whether the portion of the memory is associated with the reliability risk, a selected program scheme to be used to program the host data to the portion of the memory, wherein the selected program scheme is one of a single-fine program scheme or a partial-fine program scheme, wherein the single-fine program scheme includes performing a fine pulse for each level of cells being programmed, of multiple levels of cells being programmed, and wherein the partial-fine program scheme includes performing multiple fine pulses for only a subset of the multiple levels of cells being programmed. The memory device may execute the program command by performing the selected program scheme.

Abstract: In some implementations, a memory device may program host data to memory using a program scheme, including by permitting, during a first programming pulse, a memory cell to receive a first program voltage; and by inhibiting, during a second and third programming pulse, the memory cell from receiving a second and third program voltage, respectively. The memory device may verify the program scheme using a majority vote program verify scheme, including by performing a first, second, and third program verify procedure for the memory cell following the first, second, and third programming pulse, respectively; and by determining whether the memory cell passes a majority of the first, second, and third program verify procedures. The memory device may inhibit or permit the memory cell to receive a fourth program voltage based on whether the memory cell passes the majority of the first, second, and third program verify procedures.

Abstract: Methods, systems, and apparatuses include receiving, by a memory subsystem, a power down notification. A memory usage pattern for the memory subsystem is retrieved in response to receiving the power down notification. A power mode is selected using the current time and the memory usage pattern. The selected power mode is enabled.

Abstract: In some implementations, a memory device may detect a read command associated with reading data stored by the memory device. The memory device may determine whether the read command is from a host device in communication with the memory device. The memory device may select, based on whether the read command is from the host device, one of a first voltage pattern or a second voltage pattern to be applied to memory cells of the memory device to execute the read command, wherein the first voltage pattern is selected if the read command is from the host device and the second voltage pattern is selected if the read command is not from the host device, wherein the second voltage pattern is different from the first voltage pattern. The memory device may execute the read command using a selected one of the first voltage pattern or the second voltage pattern.

Abstract: A memory page scan on a memory page of a plurality of memory pages of a memory device is initiated. Whether an update trim flag is set is determined. A set update trim flag indicates that a second trim value is to be used for the memory page scan. A cleared update trim flag indicates that a first trim value is to be used for the memory page scan. The update trim flag is set based on a data state metric associated with a first page read and a data state metric associated with a second page read.

Abstract: Implementations described herein relate to a memory device with a fast write mode to mitigate power loss. In some implementations, the memory device may detect a condition associated with power supplied to the memory device. The memory device may detect one or more pending write operations to be performed to cause data to be written to memory cells of the memory device. The memory device may switch from a first voltage pattern, previously used by the memory device to write data to one or more memory cells of the memory device, to a second voltage pattern based on detecting the condition and based on detecting the one or more pending write operations. The memory device may perform at least one write operation, of the one or more pending write operations, using the second voltage pattern.

Abstract: A signal processing device, used to suppress cross-talk nonlinear distortion of a RF front end circuit. The first circuit generates a first PD signal and a second PD signal according to a first input signal and a second input signal. The first PD signal and the second PD signal are provided to a first PA and a second PA of the RF front end circuit. The second circuit generates a first control signal and a second control signal according to a first output signal, a second output signal, a first DPD signal and a second DPD signal, so as to control the first circuit to generate the first PD signal and the second PD signal. The first PA generates the first output signal through a first filter having a first operating BW. The second PA generates the second output signal through a second filter having a second operating BW.

Abstract: A memory subsystem receives a first read command and a second read command. Responsive to determining that the first read command originated from a host system, the memory subsystem selects a reverse read trim setting. Responsive to determining that the second read command did not originate from the host system, the memory subsystem selects a forward read trim setting. The memory subsystem executes the first read command using the reverse read trim setting. The memory subsystem executes the second read command using the forward read trim setting.

Abstract: Methods, systems, and apparatuses include determining an operation type for an operation. A sensing time is elected using the operation type. The operation is executed using the sensing time.

Abstract: A method includes determining that a program operation includes a first pass to apply a first voltage distribution to a plurality of memory cells and a second pass to apply a second voltage distribution to the plurality of memory cells, performing the first pass of the program operation using a first sensing time, and performing the second pass of the program operation using a second sensing time during the second pass of the program operation, where the first sensing time is shorter than the second sensing time.

Abstract: Programming data in memory is described herein. An example apparatus includes an array of memory cells having a plurality of access lines to which the cells are coupled, and a processing device that performs a program operation on the array, including programming data to be stored in one page of cells of the array to the cells of the array coupled to a first one of the access lines, programming additional data to be stored in that page to the cells of the array coupled to a second one of the access lines adjacent to the first one of the access lines, sensing the data programmed to the cells of the array coupled to the first one of the access lines, and programming data to be stored in two pages of cells of the array to the cells of the array coupled to the first one of the access lines.

Abstract: Methods, systems, and devices for concurrent read error handling operations are described. A system may perform a read error handling procedure in which operations may be performed concurrently or in succession. For example, a second read operation may be initiated while error control is being performed for a first read operation, or while data from the first read operation is being transferred to a controller. Further, the second read operation may be terminated based on identifying one or more errors in the data from the first read operation, such that the read error handling procedure may be terminated without finishing active processes of the read error handling procedure. Additionally, the system may be configured to perform the read error handling procedure such that a channel activation operation and a channel deactivation operation may be performed at the beginning and end of the read error handling procedure, respectively.

Abstract: In some implementations, a memory device may receive a program command instructing the memory device to program host data to a word line associated with a memory. The memory device may determine a program erase cycle (PEC) count associated with the word line. The memory device may determine, based on the PEC count, a selected program scheme to be used to program the host data to the word line, wherein the selected program scheme is one of a single-fine program scheme or a multi-fine program scheme. The memory device may execute the program command by performing the selected program scheme.

Abstract: Devices, methods, and systems for performing corrective sense operations in memory are described herein. An example apparatus includes a memory component including a plurality of groups of memory cells, and a processing device coupled to the memory component and configured to perform a sense operation on the plurality of groups of memory cells, perform a corrective sense operation on a first one of the plurality of groups of memory cells using a corrective value, and perform the corrective sense operation on a second one of the plurality of groups of memory cells using the corrective value.

Abstract: Methods, systems, and devices for a ganged read operation for multiple sub-blocks are described. The method may include writing a respective first logic state to each memory cell of a set of memory portions and biasing a first word line and a second word line to a first voltage. In some examples, the first word line may correspond to a first memory portion and the second word line may correspond to a second memory portion. Further, the method may include applying a first read pulse to the first word line and a second read pulse to the second word line and reading a second logic state from one or more memory cells of the first memory portion and the second memory portion. Further, the method may include validating the write operation based on reading the second logic state from the memory cells of the first memory portion and the second memory portion.

Abstract: Methods, systems, and apparatuses include receiving a command directed to a portion of memory. A cycle number for the portion of memory is determined. A group to which the portion of memory belongs is determined. A bitline voltage is determined using the cycle number and the group. The command is executed using the bitline voltage.

Abstract: A program command specifying new data to be programmed is received and partitioned into a plurality of data partitions. A wordline addressing a first set of memory cells to be programmed with a data partition of the plurality of data partitions is identified for a specified block of the memory device. Existing data stored by a second set of memory cells is read. An expected data state metrics is produced for each data partition of the plurality of data partitions. A data partition associated with a lowest expected data state metric among the plurality of expected data state metrics is identified. The identified data partition is programmed to the identified wordline.

Abstract: Implementations described herein relate to a memory device with a fast write mode to mitigate power loss. In some implementations, the memory device may detect a condition associated with power supplied to the memory device. The memory device may detect one or more pending write operations to be performed to cause data to be written to memory cells of the memory device. The memory device may switch from a first voltage pattern, previously used by the memory device to write data to one or more memory cells of the memory device, to a second voltage pattern based on detecting the condition and based on detecting the one or more pending write operations. The memory device may perform at least one write operation, of the one or more pending write operations, using the second voltage pattern.