Abstract: A wafer structure with an electroless plating metal connecting layer and a method for fabricating the same are proposed. A wafer has an active surface and an inactive surface opposite to the active surface. The active surface has a plurality of electrical connecting pads formed thereon. An insulating protective layer is formed on the active surface of the wafer and a plurality of openings are formed in the insulating protective layer to correspond to the electrical connecting pads, so that the electrical connecting pads are exposed. A plurality of electroless plating metal connecting layers are formed on the electrical connecting pads that are exposed through the openings, by electroless plating. Therefore, the electrical connecting process of the wafer is simplified and easily implemented. As a result, the production cost is reduced, the yield is raised, and mass production of high quality is ensured simultaneously.

Abstract: A stack structure of a carrier board embedded with semiconductor components and a method for fabricating the same are proposed. The stack structure includes first and second carrier boards having a through hole respectively, first and second semiconductors component disposed in through holes of the first and second semiconductor components respectively, and a dielectric layer structure clamped between the first carrier board and the second carrier board and having a first dielectric layer formed on the first carrier board and an inactive surface of the first semiconductor component and filled in gaps between the first carrier board and the first semiconductor component, a second dielectric layer formed on the second carrier board and an inactive of the second semiconductor component and filled in gaps between the second carrier board and the second semiconductor component, and a bonding layer clamped between the first dielectric layer and the second dielectric layer.