Abstract: A touch-sensing liquid crystal display is provided and includes a display panel and a backlight module. The display panel includes a transistor substrate, a liquid crystal layer and a common electrode. The liquid crystal layer is disposed on the transistor substrate. The common electrode is disposed on the liquid crystal layer. The transistor substrate includes data lines, scan lines, pixel units and a shield layer. The data lines are used to receive first signals. The scan lines are used to receive second signals. The pixel units include pixel electrodes and transistor switches, in which the transistor switches are electrically connected to the data lines, the scan lines and the pixel electrodes. The shield layer is disposed between the pixel electrodes and the transistor switches. The backlight module is disposed on the display panel, in which the liquid crystal layer is sandwiched between the shield layer and the backlight module.

Abstract: An active device array substrate for saving material cost includes a substrate, scan lines, data lines, a thin film transistor, a color filter layer, a transparent conductive layer, an insulating layer and a pixel electrode. The color filter layer covers and contacts the scan lines, data lines and the thin film transistor. The transparent conductive layer is disposed on the color filter layer and electrically isolated from the scan lines, the data lines and the thin film transistor by the color filter layer. The insulating layer covers the transparent conductive layer. The pixel electrode is disposed on the insulating layer and connected to the thin film transistor.

Abstract: A liquid crystal display includes a bottom substrate, at least one thin film transistor, an overcoat layer, a bottom common electrode, at least one pixel electrode and a liquid crystal layer. The thin film transistor is disposed on the bottom substrate, including a gate electrode, a source electrode and a drain electrode. The overcoat layer is disposed above the thin film transistor. The bottom common electrode is disposed on the overcoat layer. The pixel electrode is disposed above the bottom common electrode and electrically connected to the drain electrode. The liquid crystal layer is disposed above the pixel electrode.

Abstract: An active device array substrate and a display panel are provided. The active device array substrate includes a substrate, a first conductor layer, a gate dielectric layer, a second conductor layer, an overcoat layer, a transparent electrode, a capacitive layer and pixel electrodes. The first conductor layer includes gate lines and light-shielding patterns. The gate dielectric layer covers the first conductor layer. The second conductor layer includes data lines and drain electrodes. Each of the data lines correspondingly overlaps one of the light-shielding patterns. The transparent electrode covers the overcoat layer. The pixel electrode is disposed on the capacitive layer and covers a portion of the shielding pattern. Each of the light-shielding patterns has a width greater than that of the overlapping data line. The gap between the edge of the light-shielding pattern and that of the overlapping data line is not greater than 2.5 microns.

Abstract: A shift register and a voltage adjusting circuit and method thereof are disclosed. The voltage adjusting circuit includes a first input terminal, a second input terminal, a transistor, a first capacitor, a second capacitor, and an output terminal. The first input terminal receives a second clock signal. The second input terminal receives a fourth clock signal. The transistor has a source electrode, a drain electrode, and a gate electrode. The source electrode is coupled to ground and the gate electrode is coupled to the second input terminal. The first capacitor is coupled between the drain electrode and the first input terminal. One end of second capacitor is coupled between the first capacitor and drain electrode, and the other end of second capacitor is coupled between the second input terminal and gate electrode. The output terminal is coupled between the first capacitor and drain electrode to output an adjusted voltage.

Abstract: An externally connection type USB2.0 interface flash card reader comprising an insertion cassette housing, and a USB2.0 connection cable, characterized in that one end of the insertion cassette housing is provided with an insertion/connection hole allowing the insertion of various type of solid state flash cards externally to the insertion cassette housing, and connecting to USB ports of a host computer via the USB 2.0 card.