Abstract: A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.

Abstract: A communication receiver includes a first signal processing circuit and a second signal processing circuit. The first signal processing circuit includes a first feedforward equalizer and a decision circuit. The first feedforward equalizer processes a received signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a first symbol decision signal. The second signal processing circuit includes a second feedforward equalizer, a decision feedforward equalizer, and a first decision feedback equalizer. The second feedforward equalizer processes the first equalized signal to generate a second equalized signal. The decision feedforward equalizer processes the first symbol decision signal to generate a third equalized signal. The first decision feedback equalizer generates a second symbol decision signal according to the second equalized signal and the third equalized signal.

Abstract: A semiconductor device structure is provided. The device includes one or more first semiconductor layers, each first semiconductor layer of the one or more first semiconductor layers is surrounded by a first intermixed layer, wherein the first intermixed layer comprises a first material and a second material.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate, and a dielectric wall adjacent to the first nanostructures. The semiconductor structure also includes a first liner layer between the first nanostructures and the dielectric wall, and the first liner layer is in direct contact with the dielectric wall. The semiconductor structure also includes a gate structure surrounding the first nanostructures, and the first liner layer is in direct contact with a portion of the gate structure.

Abstract: A semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. The backside source contact extends through the bottom dielectric layer.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first channel structure configured to transport charge carriers within a first transistor device and a first gate electrode layer wrapping around the first channel structure. A second channel structure is configured to transport charge carriers within a second transistor device. A second gate electrode layer wraps around the second channel structure. The second gate electrode layer continuously extends from around the second channel structure to cover the first gate electrode layer. A third channel structure is configured to transport charge carriers within a third transistor device. A third gate electrode layer wraps around the third channel structure. The third gate electrode layer continuously extends from around the third channel structure to cover the second gate electrode layer.

Abstract: A circuit for touch sensing includes a driving unit, a self-capacitive sensor circuit, a mutual-capacitive sensor circuit and a control circuit. The driving is configured to generate a driving signal. The self-capacitive sensor circuit is configured to generate a self-capacitance sensing result. The mutual-capacitive sensor circuit is configured to receive the driving signal in order to generate a mutual-capacitance sensing result when the voltage of a node between the self-capacitive sensor circuit and the mutual-capacitive sensor circuit reaches a reference voltage. The control circuit receives and computes the self-capacitance sensing result and the mutual-capacitance sensing result in order to generate a sensing result. By utilizing the circuit for touch sensing of present disclosure, the accuracy and the efficiency of touch sensing can be enhanced.

Abstract: A circuit for touch sensing includes a driving unit, a self-capacitive sensor circuit, a mutual-capacitive sensor circuit and a control circuit. The driving is configured to generate a driving signal. The self-capacitive sensor circuit is configured to generate a self-capacitance sensing result. The mutual-capacitive sensor circuit is configured to receive the driving signal in order to generate a mutual-capacitance sensing result when the voltage of a node between the self-capacitive sensor circuit and the mutual-capacitive sensor circuit reaches a reference voltage. The control circuit receives and computes the self-capacitance sensing result and the mutual-capacitance sensing result in order to generate a sensing result. By utilizing the circuit for touch sensing of present disclosure, the accuracy and the efficiency of touch sensing can be enhanced.

Abstract: A method for calculating a touch coordinate on a touch panel is provided, the touch panel having a plurality of points, said method comprising: determining a group of candidate points when a touch occurs on the touch panel, each candidate point having one sensing value; assigning weights to the sensing values of the respective candidate points to obtain weighted sensing values; and calculating a coordinate by utilizing the weighted sensing values and positions of the respective candidate points. By using said method, the calculation result of the touch coordinate will be more stable.

Abstract: A method for calculating a touch coordinate on a touch panel is provided, the touch panel having a plurality of points, said method comprising: determining a group of candidate points when a touch occurs on the touch panel, each candidate point having one sensing value; assigning weights to the sensing values of the respective candidate points to obtain weighted sensing values; and calculating a coordinate by utilizing the weighted sensing values and positions of the respective candidate points. By using said method, the calculation result of the touch coordinate will be more stable.