Patents by Inventor Chung-Ling Huang

Chung-Ling Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240081081
    Abstract: A ferroelectric memory device and a semiconductor die are provided. The ferroelectric memory device includes a gate electrode; a channel layer, overlapped with the gate electrode; source/drain contacts, in contact with separate ends of the channel layer; a ferroelectric layer, lying between the gate electrode and the channel layer; and a first insertion layer, extending in between the ferroelectric layer and the channel layer, and comprising a metal carbonitride or a metal nitride.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Ling Lee, Chung-Te Lin, Han-Ting Tsai, Wei-Gang Chiu, Yen-Chieh Huang, Ming-Yi Yang
  • Patent number: 11923358
    Abstract: A device comprises a first transistor, a second transistor, a first contact, and a second contact. The first transistor comprises a first gate structure, first source/drain regions on opposite sides of the first gate structure, and first gate spacers spacing the first gate structure apart from the first source/drain regions. The second transistor comprises a second gate structure, second source/drain regions on opposite sides of the second gate structure, and second gate spacers spacing the second gate structure apart from the second source/drain regions. The first contact forms a first contact interface with one of the first source/drain regions. The second contact forms a second contact interface with one of the second source/drain regions. An area ratio of the first contact interface to top surface the first source/drain region is greater than an area ratio of the second contact interface to top surface of the second source/drain region.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Pin Huang, Hou-Yu Chen, Chuan-Li Chen, Chih-Kuan Yu, Yao-Ling Huang
  • Patent number: 7920724
    Abstract: The present invention disclose an iris recognition method, which utilizes a matching pursuit algorithm to simplify the extraction and reconstruction of iris features and reduce the memory space required by each iris feature vector without the penalty of recognition accuracy. The iris recognition method of the present invention comprises an iris-localization component and a pattern matching component. The iris-localization component locates the iris region via the color difference between different portions of the eyeball. The primary iris features are extracted from iris information and transformed into a sequence of iris feature vectors by a matching pursuit algorithm. Thus, the iris image can be represented by a sequence of atoms, and each atom contains base, amplitude and location. Then, the comparison between the feature vectors of two irises is performed to determine whether the two irises match.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: April 5, 2011
    Assignee: National Chiao Tung University
    Inventors: Wen-Gang Che, Jian-Liang Lin, Wen-Liang Hwang, Chung-Ling Huang