Abstract: A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a substrate, lightly doped source/drain regions formed in the substrate aligned to the gate structure, sidewall spacers formed on the sidewalls of the gate structure and overlying the lightly doped source/drain regions, deeper source/drain diffusions formed into the substrate aligned to the sidewall spacers and additional pocket implants of source/drain dopants formed at the boundary of the deeper source/drain diffusions and the substrate. In a preferred method, the additional pocket implants are formed using an angled ion implant with the angle being between 4 and 45 degrees from vertical. Additional embodiments include recesses formed in the source/drain regions and methods for forming the recesses.

Abstract: Silicon on insulator (SOI) devices and methods for fabricating the same are provided. An exemplary embodiment of a SOI device comprises a substrate. A first insulating layer is formed over the substrate. A plurality of semiconductor islands is formed over the first insulating layer, wherein the semiconductor islands are isolated from each other. A second insulating layer is formed over the first insulating layer, protruding over the semiconductor islands and surrounding thereof. At least one recess is formed in a portion of the second insulating layer adjacent to a pair of the semiconductor islands. A first dielectric layer is formed on a portion of each of the semiconductor islands. A conductive layer is formed over the first dielectric layer and over the second insulating layer exposed by the recess. A pair of source/drain regions is oppositely formed in portions of each of the semiconductor islands not covered by the first dielectric layer and the conductive layer.

Abstract: A method of forming a semiconductor structure includes providing a semiconductor substrate comprising a first region and a second region, forming a first PMOS device in the first region wherein a first gate electrode of the first PMOS device has a first p-type impurity concentration, forming a stress memorization layer over the first PMOS device, reducing the stress memorization layer in the first region, performing an annealing after the step of reducing the stress memorization layer in the first region, and removing the stress memorization layer. The same stress memorization layer is not reduced in a region having an NMOS device. The same stress memorization layer may not be reduced in a region including a second PMOS device.

Abstract: A semiconductor device with a recessed L-shaped spacer and a method for fabricating the same. A recessed L-shaped spacer includes a vertical portion and a horizontal portion. The vertical portion is disposed on lower sidewalls of a conductor pattern, exposing upper sidewalls thereof. A top spacer is on the L-shaped spacer, wherein a width ratio of the vertical portion of the L-shaped spacer to the top spacer is at least about 2:1.

Abstract: A method for cleaning and forming an oxide film on a surface, particularly a silicon surface. The surface is initially cleaned and then exposed to ozone vapor, which forms the oxide film on the surface. The method is particularly useful for forming a pre-liner oxide film on trench surfaces in the fabrication of STI (shallow trench isolation) structures.

Abstract: A dummy region varactor for improving a CMP process and improving electrical isolation from active areas and a method for forming the same, the varactor including a semiconductor substrate having a dummy region said dummy region including a first well region having a first polarity; shallow trench isolation (STI) structures disposed in the dummy region defining adjacent mesa regions comprising first, second, and third mesa regions; a second well region having a second polarity underlying the first mesa region having the second polarity to form a PN junction interface; wherein said second and third mesa regions having the first polarity are formed adjacent either side of said first mesa region.

Abstract: Provided are a fuse structure and a method for manufacturing the fuse structure. In one example, the method includes providing a multilayer interconnect structure (MLI) over a semiconductor substrate. The MLI includes multiple fuse connection and bonding connection features. A passivation layer is formed over the MLI and patterned to form openings, with each opening being aligned with one of the fuse connection or bonding connection features. A conductive layer is formed on the passivation layer and in the openings. The conductive layer is patterned to form bonding features and fuse structures. Each bonding feature is in contact with one of the bonding connection features, and each fuse structure is in contact with two of the fuse connection features. A cap dielectric layer is formed over the fuse structures and patterned to expose at least one of the bonding features while leaving the fuse structures covered.

Abstract: A method for forming a FIN-FET device employs a blanket planarizing layer formed upon a blanket topographic gate electrode material layer. The blanket planarizing layer is patterned and employed as a mask layer for patterning the blanket topographic gate electrode material layer to form a gate electrode. Since the blanket planarizing layer is formed as a planarizing layer, a photoresist layer formed thereupon is formed with enhanced resolution. As a result, the gate electrode is also formed with enhanced resolution. A resulting FIN-FET structure has the patterned planarizing layer formed in an inverted “U” shape upon the gate electrode.

Abstract: A method for forming a FIN-FET device employs a blanket planarizing layer formed upon a blanket topographic gate electrode material layer. The blanket planarizing layer is patterned and employed as a mask layer for patterning the blanket topographic gate electrode material layer to form a gate electrode. Since the blanket planarizing layer is formed as a planarizing layer, a photoresist layer formed thereupon is formed with enhanced resolution. As a result, the gate electrode is also formed with enhanced resolution. A resulting FIN-FET structure has the patterned planarizing layer formed in an inverted “U” shape upon the gate electrode.

Abstract: A method for cleaning and forming an oxide film on a surface, particularly a silicon surface. The surface is initially cleaned and then exposed to ozone vapor, which forms the oxide film on the surface. The method is particularly useful for forming a pre-liner oxide film on trench surfaces in the fabrication of STI (shallow trench isolation) structures.

Abstract: A method for forming a FIN-FET device employs a blanket planarizing layer formed upon a blanket topographic gate electrode material layer. The blanket planarizing layer is patterned and employed as a mask layer for patterning the blanket topographic gate electrode material layer to form a gate electrode. Since the blanket planarizing layer is formed as a planarizing layer, a photoresist layer formed thereupon is formed with enhanced resolution. As a result, the gate electrode is also formed with enhanced resolution. A resulting FIN-FET structure has the patterned planarizing layer formed in an inverted “U” shape upon the gate electrode.