Abstract: A multi-chip stack structure and a method for fabricating the same are provided.

Abstract: A multi-chip stack structure and a method for fabricating the same are provided.

Abstract: A multi-chip stack structure and a method for fabricating the same are provided.

Abstract: A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires.

Abstract: A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires.

Abstract: A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires.

Abstract: A semiconductor package with stacked chips and a method for fabricating the same are proposed. The semiconductor package includes a lead frame having a plurality of leads and supporting extensions; at least one preformed package having an active surface, and a non-active surface attached to the supporting extensions of the lead frame; at least one chip mounted on the active surface of the preformed package; a plurality of bonding wires for electrically interconnecting the lead frame, the preformed package and the chip; and an encapsulant for encapsulating the preformed package, the chip, the bonding wire and a portion of the lead frame. The active surface of the preformed package serves for carrying the chip and can be used as a wire jumper, so as to solve a known good die (KGD) problem of a multi-chip module.

Abstract: A multi-chip stack structure and a method for fabricating the same are provided.

Abstract: A multi-chip stack structure and a manufacturing method thereof are provided. The fabrication method includes the steps of: providing a chip carrier having a first surface and a second surface opposing thereto and at least a first chip and a second chip mounted on the first surface; electrically connecting the chips to the chip carrier by a plurality of bonding wires; and stacking at least a third chip on the first and second chips by a film deposed therebetween, wherein the third chip is stepwise stacked on the first chip and at least a part of the bonding wire connected to the second chip is covered by the film, and electrically connecting the third chip and the chip carrier by a bonding wire, thereby enabling a plurality of chips to be stacked on the chip carrier to enhance the electrical performance of electronic products.

Abstract: The present invention proposes a multi-chip semiconductor device having leads and a method for fabricating the same. The method includes the steps of: providing a substrate having a plurality of connection pads disposed on a surface thereof; mounting a plurality of semiconductor chips on the surface of the substrate, and electrically connecting the semiconductor chips to the surface of the substrate; forming an encapsulant on the substrate to encapsulate the semiconductor chips and expose the connection pads to form a package unit; and providing a lead frame having a plurality of leads, and electrically connecting the connection pads exposed from the package unit to the leads of the lead frame to form a multi-chip semiconductor device having leads, thereby forming a multi-chip semiconductor device having leads.

Abstract: A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires.

Abstract: The present invention provides a fabrication method of a multi-chip stacking structure. The method includes steps of: stacking the first chips on the chip carrier in a step-like manner to form a first chip module; electrically connecting the first chip module to the chip carrier by a plurality of first bonding wires; stacking the second chips on the first chip module in step-like manner to form a second chip module, wherein a bottom chip of the second chip module is stacked on a top chip of the first chip module by an adhesive layer with the bottom chip deviated from the top chip horizontally in a direction toward the first bonding wires; and electrically connecting the bond pads of the second chip module to the chip carrier by a plurality of second bonding wires.

Abstract: The present invention provides a multi-chip stacking structure. The multichip stacking structure comprises: a chip carrier; a first and a second chip modules respectively having a plurality of first and a plurality of second chips, wherein each chips has a bond pad and the chips are stacked on the chip carrier in a step-like manner to expose the bond pads; and a plurality of bonding wires for electrically connecting the bond pads of the first and the second chip modules to the chip carrier, wherein a bottom chip of the second chip module is stacked on a top chip of the first chip module by an adhesive layer having fillers therein to support the bottom chip, and the bottom chip is deviated from the top chip horizontally in a direction toward the bonding wires of the first chip module.

Abstract: A and method for fabricating a warpage-preventive circuit board is provided, wherein a plurality of conductive traces are formed on a surface of an electrically-insulative core layer, and a plurality of discontinuous dummy circuit regions are disposed on the surface of the electrically-insulative core layer at area free of the conductive traces, with adjacent dummy circuit regions being spaced apart by at least a chink. During a high-temperature fabrication process, the dummy circuit regions help reduce thermal stress and the chinks absorb thermal expansion of the dummy circuit regions, to thereby prevent warpage of the circuit board and cracks of a chip mounted on the circuit board, such that yield and reliability of fabricated semiconductor devices can be improved.

Abstract: A semiconductor package with stacked chips and a method for fabricating the same are proposed. The semiconductor package includes a lead frame having a plurality of leads and supporting extensions; at least one preformed package having an active surface, and a non-active surface attached to the supporting extensions of the lead frame; at least one chip mounted on the active surface of the preformed package; a plurality of bonding wires for electrically interconnecting the lead frame, the preformed package and the chip; and an encapsulant for encapsulating the preformed package, the chip, the bonding wire and a portion of the lead frame. The active surface of the preformed package serves for carrying the chip and can be used as a wire jumper, so as to solve a known good die (KGD) problem of a multi-chip module.

Abstract: A semiconductor package with stacked chips and a method for fabricating the same are proposed. The semiconductor package includes a lead frame having a plurality of leads and supporting extensions; at least one preformed package having an active surface, and a non-active surface attached to the supporting extensions of the lead frame; at least one chip mounted on the active surface of the preformed package; a plurality of bonding wires for electrically interconnecting the lead frame, the preformed package and the chip; and an encapsulant for encapsulating the preformed package, the chip, the bonding wire and a portion of the lead frame. The active surface of the preformed package serves for carrying the chip and can be used as a wire jumper, so as to solve a known good die (KGD) problem of a multi-chip module.

Abstract: A semiconductor package with stacked chips and a method for fabricating the same are proposed. The semiconductor package includes a lead frame having a plurality of leads and supporting extensions; at least one preformed package having an active surface, and a non-active surface attached to the supporting extensions of the lead frame; at least one chip mounted on the active surface of the preformed package; a plurality of bonding wires for electrically interconnecting the lead frame, the preformed package and the chip; and an encapsulant for encapsulating the preformed package, the chip, the bonding wire and a portion of the lead frame. The active surface of the preformed package serves for carrying the chip and can be used as a wire jumper, so as to solve a known good die (KGD) problem of a multi-chip module.

Abstract: A multi-chip module is proposed, which is designed to pack two or more semi-conductor chips in a stacked manner over a chip carrier in a single package. The multi-chip module is characterized by the use of adhesive with fillers to allow the topmost chip (i.e. the second chip) superimposed to the bottommost chip (i.e. the first chip) after the first chip electrically connected to the chip carrier. The thickness of the adhesive layer depends on the diameter of the fillers higher than loop height of the bonding wires that is positioned above the active surface of the first chip to prevent the bonding wires connected to the first chip to come in contact with the overlaid chip.

Abstract: A warpage-preventive circuit board and method for fabricating the same is provided, wherein a plurality of conductive traces are formed on a surface of an electrically-insulative core layer, and a plurality of discontinuous dummy circuit regions are disposed on the surface of the electrically-insulative core layer at area free of the conductive traces, with adjacent dummy circuit regions being spaced apart by at least a chink. During a high-temperature fabrication process, the dummy circuit regions help reduce thermal stress and the chinks absorb thermal expansion of the dummy circuit regions, to thereby prevent warpage of the circuit board and cracks of a chip mounted on the circuit board, such that yield and reliability of fabricated semiconductor devices can be improved.

Abstract: A warpage-preventive circuit board and method for fabricating the same is provided, wherein a plurality of conductive traces are formed on a surface of an electrically-insulative core layer, and a plurality of discontinuous dummy circuit regions are disposed on the surface of the electrically-insulative core layer at area free of the conductive traces, with adjacent dummy circuit regions being spaced apart by at least a chink. During a high-temperature fabrication process, the dummy circuit regions help reduce thermal stress and the chinks absorb thermal expansion of the dummy circuit regions, to thereby prevent warpage of the circuit board and cracks of a chip mounted on the circuit board, such that yield and reliability of fabricated semiconductor devices can be improved.