Abstract: A sensor membrane structure is provided. The sensor membrane structure includes a substrate, a first insulating layer, and a device layer. The substrate has a first surface and a second surface that is opposite to the first surface. A cavity is formed on the first surface, an opening is formed on the second surface, and the cavity communicates with the opening. The cavity and the opening penetrate the substrate in a direction that is perpendicular to the first surface. The first insulating layer is disposed on the first surface of the substrate. The device layer is disposed on the first insulating layer. The first insulating layer is disposed for protecting the sensor membrane structure from overetched and remain stable during the etching process, increasing the yield of the sensor membrane structure.

Abstract: A sensor membrane structure is provided. The sensor membrane structure includes a substrate, a first insulating layer, and a device layer. The substrate has a first surface and a second surface that is opposite to the first surface. A cavity is formed on the first surface, an opening is formed on the second surface, and the cavity communicates with the opening. The cavity and the opening penetrate the substrate in a direction that is perpendicular to the first surface. The first insulating layer is disposed on the first surface of the substrate. The device layer is disposed on the first insulating layer.

Abstract: A mask ROM fabrication method which comprises steps: sequentially forming a gate dielectric layer and a first photoresist layer on a substrate; letting a light having a wavelength of 365 nm pass through a first phase shift mask to photolithographically form on the first photoresist layer a plurality of first trenches having a width of 243-365 nm; doping the substrate to form a plurality of embedded bit lines having a width of 243-365 nm; removing the first photoresist layer; sequentially forming a polysilicon layer and a second photoresist layer on the gate dielectric layer; and letting the light pass through a second phase shift mask to photolithographically form a plurality of polysilicon word lines on the polysilicon layer. Thereby is reduced the line width of mask ROM to 243-365 nm and decreased the area of mask ROM.

Abstract: A mask ROM fabrication method which comprises steps: sequentially forming a gate dielectric layer and a first photoresist layer on a substrate; letting a light having a wavelength of 365 nm pass through a first phase shift mask to photolithographically form on the first photoresist layer a plurality of first trenches having a width of 243-365 nm; doping the substrate to form a plurality of embedded bit lines having a width of 243-365 nm; removing the first photoresist layer; sequentially forming a polysilicon layer and a second photoresist layer on the gate dielectric layer; and letting the light pass through a second phase shift mask to photolithographically form a plurality of polysilicon word lines on the polysilicon layer. Thereby is reduced the line width of mask ROM to 243-365 nm and decreased the area of mask ROM.