Patents by Inventor Chung-Lung Kevin Shum

Chung-Lung Kevin Shum has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6865645
    Abstract: A method of supporting programs that include instructions that modify subsequent instructions in a multi-processor system with a central processing unit including an execution unit, and instruction unit and a plurality of caches including a separate instruction and operand cache.
    Type: Grant
    Filed: October 2, 2000
    Date of Patent: March 8, 2005
    Assignee: International Business Machines Corporation
    Inventors: Chung-Lung Kevin Shum, Dean G. Bair, Charles F. Webb, Mark A. Check, John S. Liptay
  • Patent number: 6745313
    Abstract: A method is disclosed for selecting data in a computer system having a cache memory and a branch history table, where the method includes predicting an address corresponding to the data, selecting data at the predicted address in the cache memory, translating an address corresponding to the data, comparing the translated address with the predicted address, and if they are different, re-selecting data at the translated address in the cache memory and appending the translated address to the branch history table.
    Type: Grant
    Filed: January 9, 2002
    Date of Patent: June 1, 2004
    Assignee: International Business Machines Corporation
    Inventors: John S. Liptay, Mark A. Check, Brian R. Prasky, Chung-Lung Kevin Shum
  • Publication number: 20030131212
    Abstract: A method is disclosed for selecting data in a computer system having a cache memory and a branch history table, where the method includes predicting an address corresponding to the data, selecting data at the predicted address in the cache memory, translating an address corresponding to the data, comparing the translated address with the predicted address, and if they are different, re-selecting data at the translated address in the cache memory and appending the translated address to the branch history table.
    Type: Application
    Filed: January 9, 2002
    Publication date: July 10, 2003
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John S. Liptay, Lynne M. Liptay, Mark A. Check, Brian R. Prasky, Chung-Lung Kevin Shum
  • Patent number: 6560687
    Abstract: To support a new processor control bit, the Real Space Control (RSC) bit, in a processor system with an existing translation lookaside buffer, an existing control bit, the Private Space bit, in the translation lookaside buffer is redefined as an Ignore Common segment bit to create new non-overlapping translation lookaside buffer entries.
    Type: Grant
    Filed: October 2, 2000
    Date of Patent: May 6, 2003
    Assignee: International Business Machines Corporation
    Inventors: Aaron Tsai, Chung-Lung Kevin Shum, Dean G. Bair, Rebecca S. Wisniewski, Charles F. Webb
  • Patent number: 6233655
    Abstract: A computer processor has an I-unit (instruction unit) and instruction decoder, an E-unit (execution unit), a Buffer Control Element (BCE) containing a unified two-way interleaved L1 cache and providing write control to said two-way interleaved L1 cache. The processor has Double Word wide execution dataflow. An instruction decoder receiving instruction data from a unified cache before decoding causes, for stores, I-unit logic to initiate a request ahead of execution to tell the buffer control element that stores will be made from the E-unit, and E-unit logic sends a store request to initiate a store after decoding corresponding instruction data which indicates what address in the cache the DoubleWord data is to be stored to.
    Type: Grant
    Filed: April 30, 1998
    Date of Patent: May 15, 2001
    Assignee: International Business Machines Corporation
    Inventors: Chung-Lung Kevin Shum, Wen He Li, Charles Franklin Webb
  • Patent number: 6219758
    Abstract: A central processor uses virtual addresses to access data via cache logic including a DAT and ART, and the cache logic accesses data in the hierarchical storage subsystem using absolute addresses to access data, a part of the first level of the cache memory includes a translator for virtual or real addresses to absolute addresses. When requests are sent for a data fetch and the requested data are not resident in the first level of cache the request for data is delayed and may be forwarded to a lower level of said hierarchical memory, and a delayed request may result in cancellation of any process during a delayed request that has the ability to send back an exception. A delayed request may be rescinded if the central processor has reached an interruptible stage in its pipeline logic at which point, a false exception is forced clearing all I the wait states while the central processor ignores the false exception.
    Type: Grant
    Filed: March 25, 1998
    Date of Patent: April 17, 2001
    Assignee: International Business Machines Corporation
    Inventors: Jennifer Almoradie Navarro, Barry Watson Krumm, Chung-Lung Kevin Shum, Pak-kin Mak, Michael Fee