Patents by Inventor Chung-min Fu

Chung-min Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8577717
    Abstract: A method and a system for predicting shrinkable yield for business assessment of integrated circuit design shrink are provided. An assessment system is provided to determine cost benefits of a design shrink of an integrated circuit chip. A cost benefit analysis across different design shrink technologies is provided early in the process, so that business decisions regarding employment of design shrinks can be made as early as possible.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: November 5, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Min Fu, Yu-Chyi Harn
  • Publication number: 20130267047
    Abstract: The present disclosure provides a method. The method includes obtaining an integrated circuit (IC) layout. The method includes providing a polishing process simulation model. The method includes performing a lithography pattern check (LPC) process to the IC layout. The LPC process is performed at least in part using the polishing process simulation model. The method includes detecting, in response to the LPC process, possible problem areas on the IC layout. The method includes modifying the polishing process simulation model. The method includes repeating the performing the LPC process and the detecting the possible problem areas using the modified polishing process simulation model.
    Type: Application
    Filed: April 10, 2012
    Publication date: October 10, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: I-Chang Shih, Chung-min Fu, Ying-Chou Cheng, Yung-Fong Lu, Feng-Yuan Chiu, Chiu Hsiu Chen
  • Publication number: 20130212544
    Abstract: A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, processing the model in a computer processor to generate a temperature map containing temperatures at a plurality of points of the 3D-IC under the operating condition; identifying an electromigration (EM) rating factor, and calculating and outputting from the processor data representing a temperature-dependent EM current constraint at each point.
    Type: Application
    Filed: May 22, 2012
    Publication date: August 15, 2013
    Inventors: Chi-Yeh YU, Chung-Min FU, Ping-Heng YEH
  • Publication number: 20130132913
    Abstract: Apparatus includes a machine readable storage medium for storing a template library having at least one template. The template is to include a first layout representation of at least one pattern to be formed by multi-patterning a single layer of an IC. The pattern has a plurality of portions to be formed using a plurality of respectively different photomasks. The first layout representation includes data identifying on which photomask each portion is to be located. An electronic design automation (EDA) tool includes a processor configured to receive a hardware description language representation of at least a part of a circuit and generate a second layout representation of the part of the circuit having a plurality of polygons. The EDA tool has a matching module that identifies and outputs an indication of whether one or more of the plurality of portions matches a subset of the plurality of polygons.
    Type: Application
    Filed: November 23, 2011
    Publication date: May 23, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Min FU, Yung-Fong LU, Wen-Ju YANG, Chin-Chang HSU
  • Publication number: 20130091476
    Abstract: A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.
    Type: Application
    Filed: October 10, 2011
    Publication date: April 11, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huang-Yu CHEN, Yuan-Te HOU, Chung-Min FU, Chung-Hsing WANG, Wen-Hao CHEN, Yi-Kan CHENG
  • Publication number: 20130024832
    Abstract: A utility includes a design-for-manufacturing (DFM) checker configured to check layout patterns of an integrated circuit, and a layout change instruction generator configured to generate a layout change instruction based on a result generated by the DFM checker. The DFM checker and the layout change instruction generator are embodied on a non-transitory storage media. The layout change instruction specifies an identifier of a layout pattern among the layout patterns, and a respective layout change to be performed on the layout pattern.
    Type: Application
    Filed: July 19, 2011
    Publication date: January 24, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hao Chen, Zhe-Wei Jiang, Chung-Min Fu
  • Publication number: 20110016443
    Abstract: Embodiments of the present invention are a system, a computer program product, and a method for implementing an integrated circuit design. An embodiment is a method for implementing an integrated circuit design. The method comprises accessing an original electronic representation of an integrated circuit layout from a first user file, accessing a defined sensitivity index that characterizes an impact of the dummy pattern on the functional component, analyzing the impact of the dummy pattern on the functional component, determining whether the impact is within a limit of the sensitivity index, adjusting one of a plurality of features of the dummy pattern if the impact is not within the limit to form a generated electronic representation of a modified integrated circuit layout, and outputting the generated electronic representation to a second user file. The integrated circuit layout comprises a dummy pattern and a functional component.
    Type: Application
    Filed: April 20, 2010
    Publication date: January 20, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Min Fu, Meng-Fu You
  • Publication number: 20100275167
    Abstract: A method of designing an integrated circuit includes providing a standard cell database including a plurality of standard cells; providing an index file having cell-context information indexed to the plurality of standard cells; retrieving the cell-context information of one of the plurality of standard cells from the cell-context file; and applying the index information to a design of the integrated circuit.
    Type: Application
    Filed: February 18, 2010
    Publication date: October 28, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Min Fu, Yen-Pin Chen, Yung-Fong Lu
  • Publication number: 20090055782
    Abstract: A method for designing and manufacturing integrated circuits is provided. The method includes providing a modeling parameter set for manufacturing an integrated circuit; dividing the modeling parameter set into time-dependent data and time-independent data; saving substantially all time-independent data into a design library; and saving substantially all time-dependent data into a design-for-manufacturing (DFM) data kit, wherein the DFM data kit is external to the design library.
    Type: Application
    Filed: August 20, 2007
    Publication date: February 26, 2009
    Inventors: Chung-Min Fu, Yi-Kan Cheng
  • Patent number: 7378720
    Abstract: A semiconductor die having an integrated circuit region formed in a substrate comprises at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate, proximate to the integrated circuit region; and at least one registration feature formed within the at least one DCCF region. The at least one registration feature comprises a structure selected from the group consisting of a laser fuse mark, an alignment mark, and a monitor mark.
    Type: Grant
    Filed: April 3, 2007
    Date of Patent: May 27, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-min Fu, Huang-Sheng Lin, Yu-Chyi Harn, Hsien-Wei Chen
  • Patent number: 7356787
    Abstract: A system for defect simulation is provided. A defect layout generator generates a defect layout comprising a given number of spot defects of a given size. A processor first compares the defect layout and a provided circuit layout comprising a plurality of conductive regions. The processor further determines whether the spot defects are located on the conductive regions, and determines whether short-circuits and/or open circuits are caused by the spot defects in the conductive regions.
    Type: Grant
    Filed: April 6, 2005
    Date of Patent: April 8, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Jung Yan, Chung-Min Fu, Ricky Yang
  • Publication number: 20070276770
    Abstract: Aspects of the present invention provide a method and a system for predicting shrinkable yield for business assessment of integrated circuit design shrink. An assessment system is provided to determine cost benefits of a design shrink of an integrated circuit chip. A cost benefit analysis across different design shrink technologies is provided early in the process, so that business decisions regarding employment of design shrinks can be made as early as possible.
    Type: Application
    Filed: July 13, 2006
    Publication date: November 29, 2007
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Chung-Min Fu, Yu-Chyi Harn
  • Publication number: 20070187845
    Abstract: A semiconductor die having an integrated circuit region formed in a substrate comprises at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate, proximate to the integrated circuit region; and at least one registration feature formed within the at least one DCCF region. The at least one registration feature comprises a structure selected from the group consisting of a laser fuse mark, an alignment mark, and a monitor mark.
    Type: Application
    Filed: April 3, 2007
    Publication date: August 16, 2007
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-min Fu, Huang-Sheng Lin, Yu-Chyi Harn, Hsien-Wei Chen
  • Patent number: 7202550
    Abstract: A semiconductor die having an integrated circuit region formed in a substrate comprises at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate, proximate to the integrated circuit region; and at least one registration feature formed within the at least one DCCF region. The at least one registration feature comprises a structure selected from the group consisting of a laser fuse mark, an alignment mark, and a monitor mark.
    Type: Grant
    Filed: November 8, 2004
    Date of Patent: April 10, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-min Fu, Huang-Sheng Lin, Yu-Chyi Harn, Hsien-Wei Chen
  • Publication number: 20060230371
    Abstract: A system for defect simulation is provided. A defect layout generator generates a defect layout comprising a given number of spot defects of a given size. A processor first compares the defect layout and a provided circuit layout comprising a plurality of conductive regions. The processor further determines whether the spot defects are located on the conductive regions, and determines whether short-circuits and/or open circuits are caused by the spot defects in the conductive regions.
    Type: Application
    Filed: April 6, 2005
    Publication date: October 12, 2006
    Inventors: Jui-Jung Yan, Chung-Min Fu, Ricky Yang
  • Publication number: 20050263855
    Abstract: A semiconductor die having an integrated circuit region formed in a substrate comprises at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate, proximate to the integrated circuit region; and at least one registration feature formed within the at least one DCCF region. The at least one registration feature comprises a structure selected from the group consisting of a laser fuse mark, an alignment mark, and a monitor mark.
    Type: Application
    Filed: November 8, 2004
    Publication date: December 1, 2005
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-min Fu, Huang-Sheng Lin, Yu-Chyi Harn, Hsien-Wei Chen