Abstract: According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.

Abstract: A structure and manufacturing method of an SiC dual metal trench diode. P-type impurity is doped into the bottom of the trench layer of the dual metal trench Schottky diode to eliminate leakage current or avalanche breakdown in the corner of the trench layer in order to increase the concentration of the epitaxial layer. N-type impurity can also be doped into the region between the Schottky contact metal and the epitaxial layer to adjust the Schottky barrier and thus reduce forward voltage required for current to flow through.

Abstract: A termination structure for power trench MOS devices is disclosed. The MOS devices can be Schottky diode, IGBT or DMOS depending on what kinds of the semiconductor substrate are prepared. The termination structure comprises: a semiconductor substrate having a trench formed therein; a spacer-like MOS gate formed on a sidewall of the trench; a termination structure oxide layer formed in the trench to cover a portion of the spacer-like MOS gate and to cover a bottom of the trench; and a first electrode and a second electrode are, respectively, formed on a bottom surface and upper surface of the semiconductor substrate. The trench is formed from a boundary of the active region to an edge of the semiconductor substrate. The trench MOS devices are formed in the active region. In addition for IGBT and DMOS, the second electrode is isolated from MOS gate by an oxide layer; however, for Schottky diode, the second electrode is directed contact to the MOS gate.

Abstract: A method for forming and using silicide test structures to monitor and evaluate the quality of a semiconductive junction after the formation of a silicide layer over the junction is described. Two specially designed test structures are formed for in-line testing in the kerf of an integrated circuit wafer. The test structures comprise a silicide region formed over a diffusion region which is formed concurrently with diffusion and silicide regions which form contacts of the integrated circuit dice. The test structures are fitted with probe pads connected to semiconductive element of the junction region. A first structure is designed to measure bulk junction leakages, has the silicide contact layer spaced away from the junction edge. A second structure, designed to measure edge related junction leakage phenomena, has a serpentine edge to which the silicide layer extends and a plurality of interior openings which serve as EMMI windows.

Abstract: A method for fabricating trench MOS devices and termination structure simultaneously is disclosed. The MOS devices can be Schottky diode, IGBT or DMOS depending on the semiconductor substrate prepared. The method comprises following steps: firstly, forming a plurality of first trenches for forming the trench MOS devices in an active region, and a second trench for forming the termination structure. Thereafter, a thermal oxidation process to form a gate oxide on all areas is performed. Then, the first trenches and the second trench are refilled with a first conductive material. An etching back is carried out to remove excess first conductive material so as to form spacer in the second trench and to fill the first trenches only. Next, the gate oxide layer is removed. For IGBT or DMOS device, an extra thermal oxidation and an etching step are required to form inter-conductive oxide layer whereas for Schottky diode, these two steps are skipped.

Abstract: A method for forming and using silicide test structures to monitor and evaluate the quality of a semiconductive junction after the formation of a silicide layer over the junction is described. Two specially designed test structures are formed for in-line testing in the kerf of an integrated circuit wafer. The test structures comprise a silicide region formed over a diffusion region which is formed concurrently with diffusion and silicide regions which form contacts of the integrated circuit dice. The test structures are fitted with probe pads connected to semiconductive element of the junction region. A first structure is designed to measure bulk junction leakages, has the silicide contact layer spaced away from the junction edge. A second structure, designed to measure edge related junction leakage phenomena, has a serpentine edge to which the silicide layer extends and a plurality of interior openings which serve as EMMI windows.

Abstract: A design for a trench DMOS transistor having improved current carrying capability is presented. The principal improvement lies in the periodic replacement of the individual cells in the array with a protection cell of a different size. When this is done it becomes possible to significantly increase the density of cells per unit area. This results in a corresponding improvement in the amount of channel area available to the device and hence an increase in its current carrying capability.