Patents by Inventor Chung-Min Shih

Chung-Min Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8222113
    Abstract: A method for forming a metal-oxide-semiconductor (MOS) device includes at least steps of forming a pair of trenches in a substrate at both sides of a gate structure, filling the trenches with a silicon germanium layer by a selective epitaxy growth process, forming a cap layer on the silicon germanium layer by a selective growth process, and forming a pair of source/drain regions by performing an ion implantation process. Hence, the undesirable effects caused by ion implantation can be mitigated.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: July 17, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Shyh-Fann Ting, Shih-Chieh Hsu, Cheng-Tung Huang, Chih-Chiang Wu, Wen-Han Hung, Meng-Yi Wu, Li-Shian Jeng, Chung-Min Shih, Kun-Hsien Lee, Tzyy-Ming Cheng
  • Publication number: 20090239347
    Abstract: The present invention provides a method for forming a metal-oxide-semiconductor (MOS) device. The method includes at least the steps of forming a silicon germanium layer by the selective epitaxy growth process and forming a cap layer on the silicon germanium layer by the selective growth process. Hence, the undesirable effects caused by ion implantation can be mitigated.
    Type: Application
    Filed: May 20, 2009
    Publication date: September 24, 2009
    Applicant: United Microelectronics Corp.
    Inventors: SHYH-FANN TING, Shih-Chieh Hsu, Cheng-Tung Huang, Chih-Chiang Wu, Wen-Han Hung, Meng-Yi Wu, Li-Shian Jeng, Chung-Min Shih, Kun-Hsien Lee, Tzyy-Ming Cheng
  • Publication number: 20090224328
    Abstract: A semiconductor device includes a substrate defining an active area thereon, a shallow trench isolation on the substrate and directly surrounding the active area, a gate, a source and a drain on the active area and a hard mask on the border of the shallow trench isolation and the active area.
    Type: Application
    Filed: March 4, 2008
    Publication date: September 10, 2009
    Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Kun-Hsien Lee, Wen-Han Hung, Meng-Yi Wu, Li-Shian Jeng, Chung-Min Shih, Tzyy-Ming Cheng, Jing-Chang Wu, Tzer-Min Shen
  • Publication number: 20090186475
    Abstract: A method of manufacturing a MOS transistor, in which, a tri-layer photo resist layer is used to form a patterned hard mask layer having a sound shape and a small size, and the patterned hard mask layer is used to form a gate. Thereafter, by forming and defining a cap layer, a recess is formed through etching in the substrate. The patterned hard mask is removed after epitaxial layers are formed in the recesses. Accordingly, a conventional poly bump issue and an STI oxide loss issue leading to contact bridge can be avoided.
    Type: Application
    Filed: January 21, 2008
    Publication date: July 23, 2009
    Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Shih-Chieh Hsu, Chih-Chiang Wu, Meng-Yi Wu, Li-Shian Jeng, Chung-Min Shih, Kun-Hsien Lee, Wen-Han Hung, Yao-Chin Cheng, Chi-Sheng Tseng, Yu-Ming Lin, Shih-Jung Tu, Tzyy-Ming Cheng
  • Publication number: 20090166625
    Abstract: The present invention provides a method for forming a metal-oxide-semiconductor (MOS) device and the structure thereof. The method includes at least the steps of forming a silicon germanium layer by the first selective epitaxy growth process and forming a cap layer on the silicon germanium layer by the second selective epitaxy growth process. Hence, the undesirable effects caused by ion implantation can be mitigated.
    Type: Application
    Filed: December 28, 2007
    Publication date: July 2, 2009
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Shyh-Fann Ting, Shih-Chieh Hsu, Cheng-Tung Huang, Chih-Chiang Wu, Wen-Han Hung, Meng-Yi Wu, Li-Shian Jeng, Chung-Min Shih, Kun-Hsien Lee, Tzyy-Ming Cheng
  • Publication number: 20090117701
    Abstract: A method for manufacturing a MOS transistor includes performing a thermal treatment to repair damaged substrate before forming source/drain extension regions, accordingly negative bias temperature instability (NBTI) is reduced. Since the thermal treatment is performed before forming the source/drain extension regions, heat budget for forming the source/drain extension regions and junction depth and junction profile of the source/drain extension would not be affected. Therefore the provided method for manufacturing a MOS transistor is capable of reducing short channel effect and possesses a superior process compatibility.
    Type: Application
    Filed: November 1, 2007
    Publication date: May 7, 2009
    Inventors: Meng-Yi Wu, Kun-Hsien Lee, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Li-Shian Jeng, Chung-Min Shih, Yao-Chin Cheng, Tzyy-Ming Cheng
  • Publication number: 20080237734
    Abstract: A complementary metal-oxide-semiconductor (CMOS) transistor comprising a substrate, a first conductive type MOS transistor, a second conductive type MOS transistor, a buffer layer, a first stress layer and a second stress layer is provided. The substrate has a device isolation structure therein that defines a first active area and a second active area. The first conductive type MOS transistor and the second conductive type MOS transistor are respectively disposed in the first active area and the second active area of the substrate. A first nitride spacer of the first conductive type MOS transistor has a thickness greater than that of a second nitride spacer of the second conductive type MOS transistor. The buffer layer is disposed on the first conductive type MOS transistor. The first stress layer is disposed on the buffer layer. The second stress layer is disposed on the second conductive type MOS transistor.
    Type: Application
    Filed: March 29, 2007
    Publication date: October 2, 2008
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Han Hung, Cheng-Tung Huang, Kun-Hsien Lee, Shyh-Fann Ting, Li-Shian Jeng, Meng-Yi Wu, Chung-Min Shih, Tzyy-Ming Cheng, Chia-Wen Liang
  • Publication number: 20070099003
    Abstract: A titanate-containing material includes: a silicon-containing layer; and a crystalline layer of ammonium oxotrifluorotitanate formed on the silicon-containing layer. A method for making a titanate-containing material includes: immersing a silicon-containing substrate into an aqueous solution containing hexafluorotitanate radicals; and reacting the hexafluorotitanate radicals with water so as to form a crystalline layer of an oxotrifluorotitanate compound on the silicon-containing substrate.
    Type: Application
    Filed: March 24, 2006
    Publication date: May 3, 2007
    Inventors: Ming-Kwei Lee, Chung-Min Shih, Tsung-Hsiang Shih