Abstract: A phototherapy device includes a base, at least one light conversion device and a light source module. The base has an installation slot. The light conversion device is detachably arranged in the installation slot. Each light conversion device includes a plurality of light conversion patterns. The light source module is arranged on a side of the base and configured to provide an excitation beam to the light conversion patterns, so that each of the light conversion patterns emits a converted beam. In this way, the light conversion device of the phototherapy device can be replaced according to the user's needs.

Abstract: In one example, a multifunction printing device is described, which may include a scanning unit to scan a printing medium, a detection unit to determine geometry data of the printing medium based on the scanning, and an execution unit to execute a print job or a copy job to print content on the printing medium based on the geometry data of the printing medium.

Abstract: A method for forming an epitaxial layer on a substrate is disclosed. The method includes the steps of: providing a substrate into a chamber; injecting a precursor and a carrier gas to form the epitaxial layer on the substrate at a starting pressure; and pumping down the starting pressure to a second pressure according to a gradient during a cool down process in the chamber.

Abstract: A fin structure for a semiconductor device, such as a FinFET structure, has first and second semiconductor layers and an air gap between the layers. The second semiconductor layer includes a recessed portion, the air gap is located in the recessed portion, and the recessed portion has an upwardly-opening acute angle in the range from about 10° to about 55°. The air gap may prevent current leakage. A FinFET device may be manufactured by first recessing and then epitaxially re-growing a source/drain fin, with the regrowth starting over a tubular air gap.

Abstract: A method for manufacturing a semiconductor structure comprises the following steps. First, a recess is formed in a substrate. At least one wet cleaning process is performed to the recess and the substrate. Then, a baking process is performed to the recess and the substrate in an atmosphere containing H2 gas. After the baking process, a dry cleaning process is performed the recess and the substrate.

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate, a gate structure on the substrate, a spacer adjacent to the gate structure, an epitaxial layer in the substrate adjacent to two sides of the spacer, and a dislocation embedded within the epitaxial layer. Preferably, the top surface of the epitaxial layer is lower than the top surface of the substrate, and the top surface of the epitaxial layer has a V-shape.

Abstract: A fin structure for a semiconductor device, such as a FinFET structure, has first and second semiconductor layers and an air gap between the layers. The second semiconductor layer includes a recessed portion, the air gap is located in the recessed portion, and the recessed portion has an upwardly-opening acute angle in the range from about 10° to about 55°. The air gap may prevent current leakage. A FinFET device may be manufactured by first recessing and then epitaxially re-growing a source/drain fin, with the regrowth starting over a tubular air gap.

Abstract: A method for forming an epitaxial layer on a substrate is disclosed. The method includes the steps of: providing a substrate into a chamber; injecting a precursor and a carrier gas to form the epitaxial layer on the substrate at a starting pressure; and pumping down the starting pressure to a second pressure according to a gradient during a cool down process in the chamber.

Abstract: A fin structure for a semiconductor device, such as a FinFET structure, has first and second semiconductor layers and an air gap between the layers. The air gap may prevent current leakage. A FinFET device may be manufactured by first recessing and then epitaxially re-growing a source/drain fin, with the regrowth starting over a tubular air gap.

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate, a gate structure on the substrate, a spacer adjacent to the gate structure, an epitaxial layer in the substrate adjacent to two sides of the spacer, and a dislocation embedded within the epitaxial layer. Preferably, the top surface of the epitaxial layer is lower than the top surface of the substrate, and the top surface of the epitaxial layer has a V-shape.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: (a) providing a substrate; (b) forming a gate structure on the substrate; (c) performing a first deposition process to form a first epitaxial layer adjacent to the gate structure and performing a first etching process to remove part of the first epitaxial layer at the same time; and (d) performing a second etching process to remove part of the first epitaxial layer.

Abstract: A semiconductor device is provided includes a substrate, a gate structure formed on the substrate, an epitaxial source/drain structure respectively formed at two sides of the gate structure, and a boron-rich interface layer. The boron-rich interface layer includes a bottom-and-sidewall portion and a top portion, and the epitaxial source/drain structure is enclosed by the bottom-and-sidewall portion and the top portion.

Abstract: A method for fabricating interconnections with carbon nanotubes of the present invention comprises the following steps: forming a dual-layer that contains a catalytic layer and an upper covering layer on the periphery of a hole connecting with a substrate; and growing carbon nanotubes on the catalytic layer with the upper covering layer covering the carbon nanotubes. The present invention grows the carbon nanotubes between the catalytic layer and the upper covering layer. The upper covering layer protects the catalytic layer from being oxidized and thus enhances the growth of the carbon nanotubes. The carbon nanotubes are respectively connected with the lower substrate and an upper conductive wire via the catalytic layer and the upper covering layer, which results in a lower contact resistance. Moreover, the upper covering layer also functions as a metal-diffusion barrier layer to prevent metal from spreading to other materials via diffusion or other approaches.

Abstract: An organic thin film transistor includes: a gate electrode, a gate insulating film, a source electrode, a drain electrode, and an organic active layer. The organic active layer includes an organic semiconductor compound represented by the following formula (A) as defined in the specification.

Abstract: A method for fabricating interconnections with carbon nanotubes of the present invention comprises the following steps: forming a dual-layer that contains a catalytic layer and an upper covering layer on the periphery of a hole connecting with a substrate; and growing carbon nanotubes on the catalytic layer with the upper covering layer covering the carbon nanotubes. The present invention grows the carbon nanotubes between the catalytic layer and the upper covering layer. The upper covering layer protects the catalytic layer from being oxidized and thus enhances the growth of the carbon nanotubes. The carbon nanotubes are respectively connected with the lower substrate and an upper conductive wire via the catalytic layer and the upper covering layer, which results in a lower contact resistance. Moreover, the upper covering layer also functions as a metal-diffusion barrier layer to prevent metal from spreading to other materials via diffusion or other approaches.

Abstract: An organic thin film transistor includes: a gate electrode, a gate insulating film, a source electrode, a drain electrode, and an organic active layer. The organic active layer includes an organic semiconductor compound represented by the following formula (A) as defined in the specification.

Abstract: A method of fabricating an interconnect structure is described. A substrate is provided. A patterned interfacial metallic layer is formed on the substrate. An amorphous carbon insulating layer or a carbon-based insulating layer is formed covering the substrate and the interfacial metallic layer. A conductive carbon line or plug is formed in the amorphous carbon or carbon-based insulating layer electrically connected with the interfacial metallic layer. An interconnect structure is also described, including a substrate, a patterned interfacial metallic layer on the substrate, an amorphous carbon insulating layer or a carbon-based insulating layer on the substrate, and a conductive carbon line or plug disposed in the amorphous carbon or carbon-based insulating layer and electrically connected with the interfacial metallic layer.

Abstract: A method of fabricating an interconnect structure is described. A substrate is provided. A patterned interfacial metallic layer is formed on the substrate. An amorphous carbon insulating layer or a carbon-based insulating layer is formed covering the substrate and the interfacial metallic layer. A conductive carbon line or plug is formed in the amorphous carbon or carbon-based insulating layer electrically connected with the interfacial metallic layer. An interconnect structure is also described, including a substrate, a patterned interfacial metallic layer on the substrate, an amorphous carbon insulating layer or a carbon-based insulating layer on the substrate, and a conductive carbon line or plug disposed in the amorphous carbon or carbon-based insulating layer and electrically connected with the interfacial metallic layer.

Abstract: An interconnection structure is provided. The interconnection structure includes a substrate, a conductive barrier layer, a dielectric layer and a carbon nanotube. A conductive region is disposed in the substrate. The conductive barrier layer is disposed over the conductive region and the conductive barrier layer includes iron, cobalt or nickel. The dielectric layer is disposed on the substrate. The carbon nanotube is disposed in the dielectric layer to electrically connect with the conductive barrier layer.