Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes first and a second semiconductor dies. The first semiconductor die has a first surface and a second surface opposite the first surface. The first semiconductor die includes a first interface and a second interface. The second interface is arranged beside the first interface. The second interface is farther from the corresponding first edge of the first semiconductor die than the first interface. The second semiconductor die is stacked on the first semiconductor die. The semiconductor package assembly further includes a first conductive bump and a second conductive bump. The first conductive bump is disposed on the first surface of the first semiconductor die. The second conductive bump is disposed on the second surface of the first semiconductor die. The second semiconductor die is electrically coupled to the first semiconductor die by the second interface.

Abstract: A semiconductor package includes a logic die surrounded by a molding compound; a memory die disposed in proximity to the logic die; a plurality of vias around the logic die for electrically connecting the logic die to the memory die. Each of the plurality of vias has an oval shape or a rectangular shape when viewed from above. The vias have a horizontal pitch along a first direction and a vertical pitch along a second direction. The vertical pitch is greater than the horizontal pitch.