Patents by Inventor Chung-Ming Huang

Chung-Ming Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8457269
    Abstract: A clock and data recovery (CDR) architecture which includes a frequency detector, a phase detector, a phase charge pump circuit, a frequency charge pump circuit and a voltage controlled oscillator is provided. The phase detector is configured to only include four AND gates to receive and evaluate the intermediate signals, generated by the frequency detector, and accordingly generate a phase control signal. The voltage controlled oscillator is configured to output a plurality of clock signals with different phases according to the current signals outputted from the phase and frequency charge pump circuits, and select at least one of the plurality of clock signals with different phases for sampling a data signal.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: June 4, 2013
    Assignees: NCKU Research and Development Foundation, Himax Technologies Limited
    Inventors: Soon-Jyh Chang, Yen Long Lee, Chung-Ming Huang
  • Publication number: 20130108001
    Abstract: A clock and data recovery (CDR) architecture which includes a frequency detector, a phase detector, a phase charge pump circuit, a frequency charge pump circuit and a voltage controlled oscillator is provided. The phase detector is configured to only include four AND gates to receive and evaluate the intermediate signals, generated by the frequency detector, and accordingly generate a phase control signal. The voltage controlled oscillator is configured to output a plurality of clock signals with different phases according to the current signals outputted from the phase and frequency charge pump circuits, and select at least one of the plurality of clock signals with different phases for sampling a data signal.
    Type: Application
    Filed: October 27, 2011
    Publication date: May 2, 2013
    Applicants: HIMAX TECHNOLOGIES LIMITED, NCKU RESEARCH AND DEVELOPMENT FOUNDATION
    Inventors: Soon-Jyh CHANG, Yen Long Lee, CHUNG-MING HUANG
  • Publication number: 20130093609
    Abstract: A method for a successive approximation register ADC which includes at least one capacitor array and a plurality of switches is provided, in which the capacitors of the capacitor array are one-to-one corresponding to the switches. The method includes the following steps: firstly, at least one multiplexer is configured. Then, a first comparison voltage is outputted based on the terminal voltages on the terminals of the capacitor array, and a comparison result is outputted according to the first comparison voltage and a second comparison voltage. Afterwards, a sequence of comparisons is controlled based on the comparison result to enter into a sequence of comparison phases. Finally, the switches are orderly selected, by the multiplexer based on the comparison phases, to switch directly according to the comparison result.
    Type: Application
    Filed: October 12, 2011
    Publication date: April 18, 2013
    Applicants: HIMAX TECHNOLOGIES LIMITED, NCKU RESEARCH AND DEVELOPMENT FOUNDATION
    Inventors: Soon-Jyh CHANG, Guan-Ying Huang, CHUNG-MING HUANG
  • Patent number: 8390501
    Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) is disclosed. A first and second capacitor DACs receive a first and second input signals respectively. A first coarse comparator compares an output of the first capacitor DAC with a window reference voltage, a second coarse comparator compares an output of the second capacitor DAC with the window reference voltage, and a fine comparator compares the output of the first capacitor DAC with the output of the second capacitor DAC. A SAR controller receives outputs of the first and second coarse comparators to determine whether the outputs of the first and second capacitor DACs are within a predictive window determined by the window reference voltage. The SAR controller bypasses at least one phase of analog-to-digital conversion of the SAR ADC when the outputs of the first capacitor DAC and the second capacitor DAC are determined to be within the predictive window.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: March 5, 2013
    Assignees: NCKU Research and Development Foundation, Himax Technologies Limited, Himax Media Solutions, Inc.
    Inventors: Soon-Jyh Chang, Guan-Ying Huang, Chun-Cheng Liu, Chung-Ming Huang, Jin-Fu Lin, Chih-Haur Huang
  • Publication number: 20120274489
    Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) is disclosed. A first and second capacitor DACs receive a first and second input signals respectively. A first coarse comparator compares an output of the first capacitor DAC with a window reference voltage, a second coarse comparator compares an output of the second capacitor DAC with the window reference voltage, and a fine comparator compares the output of the first capacitor DAC with the output of the second capacitor DAC. A SAR controller receives outputs of the first and second coarse comparators to determine whether the outputs of the first and second capacitor DACs are within a predictive window determined by the window reference voltage. The SAR controller bypasses at least one phase of analog-to-digital conversion of the SAR ADC when the outputs of the first capacitor DAC and the second capacitor DAC are determined to be within the predictive window.
    Type: Application
    Filed: April 28, 2011
    Publication date: November 1, 2012
    Applicants: NCKU RESEARCH AND DEVELOPMENT FOUNDATION, HIMAX MEDIA SOLUTIONS, INC., HIMAX TECHNOLOGIES LIMITED
    Inventors: Soon-Jyh CHANG, Guan-Ying Huang, Chun-Cheng LIU, CHUNG-MING HUANG, Jin-Fu LIN, Chih-Haur HUANG
  • Patent number: 8228705
    Abstract: A memory cell includes a pair of sub-cells, each including an access transistor, a storage transistor, and an isolation transistor that are serially coupled in sequence with their source/drain connected. The isolation transistor is shared with a sub-cell of an adjacent memory cell and always turned off, wherein the storage transistor is always turned on. A wordline is coupled to a gate of the access transistor of each sub-cell, and complementary bit lines are respectively coupled to sources/drains of the access transistors of the pair of sub-cells, such that data bit may be accessed between the bit line and the corresponding storage transistor through the corresponding access transistor.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: July 24, 2012
    Assignees: Himax Technologies Limited, NCKU Research and Development Foundation
    Inventors: Soon-Jyh Chang, Ming-Liang Chung, Po-Ying Chen, Chung-Ming Huang
  • Publication number: 20120136619
    Abstract: A collision detecting method, an electronic device, and a computer program product thereof are provided for the electronic device having an accelerometer, a positioning module, and a communication module. The method includes obtaining a plurality of acceleration variations within each of a plurality of sampling intervals respectively detected by the accelerometer. The method also includes transforming the corresponding acceleration variations into a plurality of frequency domain signals for each sampling interval, and calculating energy and entropy of the frequency domain signals. The method further includes determining a collision has occurred if the energy and the entropy corresponding to each of a plurality of specific sampling intervals among the sampling intervals both drastically increase then drastically decrease suddenly.
    Type: Application
    Filed: December 6, 2010
    Publication date: May 31, 2012
    Applicant: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Chung-Ming Huang, Lai Tu, Shih-Yang Lin, Cheng-Jung Lin, Ming-Da Lee, Yi-Hong Chu
  • Publication number: 20120008244
    Abstract: An electrical-overstress (EOS) protection circuit for an electronic device includes series-connected resistors, a mode-control switch, and a bias circuit. The series-connected resistors are electrically coupled between an input and an output, and the mode-control switch is electrically coupled between the output and a ground. The bias circuit is electrically coupled to the input for generating a mode-control signal to control the mode-control switch. The bias circuit generates the mode-control signal in a way such that the mode-control switch is open in a normal mode and closed in an EOS mode.
    Type: Application
    Filed: September 19, 2011
    Publication date: January 12, 2012
    Applicant: HIMAX TECHNOLOGIES LIMITED
    Inventors: CHUNG-MING HUANG, TIEH-YEN CHANG, HUNG-SUI LIN
  • Publication number: 20110261604
    Abstract: A memory cell includes a pair of sub-cells, each including an access transistor, a storage transistor, and an isolation transistor that are serially coupled in sequence with their source/drain connected. The isolation transistor is shared with a sub-cell of an adjacent memory cell and always turned off, wherein the storage transistor is always turned on. A wordline is coupled to a gate of the access transistor of each sub-cell, and complementary bit lines are respectively coupled to sources/drains of the access transistors of the pair of sub-cells, such that data bit may be accessed between the bit line and the corresponding storage transistor through the corresponding access transistor.
    Type: Application
    Filed: April 22, 2010
    Publication date: October 27, 2011
    Applicants: NCKU RESEARCH AND DEVELOPMENT FOUNDATION, HIMAX TECHNOLOGIES LIMITED
    Inventors: SOON-JYH CHANG, Ming-Liang Chung, Po-Ying Chen, Chung-Ming Huang
  • Patent number: 8045306
    Abstract: An electrical-overstress (EOS) protection circuit for an electronic device includes series-connected resistors, a mode-control switch, and a bias circuit. The series-connected resistors are electrically coupled between an input and an output, and the mode-control switch is electrically coupled between the output and a ground. The bias circuit is electrically coupled to the input for generating a mode-control signal to control the mode-control switch. The bias circuit generates the mode-control signal in a way such that the mode-control switch is open in a normal mode and closed in an EOS mode.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: October 25, 2011
    Assignee: Himax Technologies Limited
    Inventors: Chung-Ming Huang, Tieh-Yen Chang, Hung-Sui Lin
  • Publication number: 20110131215
    Abstract: A process apparatus, a data scheduling method, and a computer readable medium thereof for a data schedule are provided. The process apparatus comprises a storage, a receiving interface, and a microprocessor. The microprocessor is respectively electrically connected to the storage and the receiving interface. The storage is configured to store a data scheduling structure which is constructed of a plurality of data items in an execution sequence. The receiving interface receives an input data item. The microprocessor retrieves at least one relevant data item from the data items according to the correlation information of the input data item. The microprocessor further performs a weight calculation according to the at least one relevant data item and the input data item, so as to generate at least one weight calculation result.
    Type: Application
    Filed: December 3, 2009
    Publication date: June 2, 2011
    Applicant: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Chung-Ming HUANG, Shih-Yang LIN, Chih-Hsun CHOU
  • Publication number: 20110122806
    Abstract: A data relay mobile apparatus and a data relay method for a wireless network and a computer program product thereof are provided. The wireless network comprises a first mobile node and a second mobile node. The data relay mobile apparatus receives first status information and second status information from the first mobile node and the second mobile node, respectively. The data relay apparatus relays data according to the first status information and the second status information. With the aforesaid method, the present invention can effectively reduce the problems caused from shadow fading.
    Type: Application
    Filed: December 3, 2009
    Publication date: May 26, 2011
    Applicant: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Chung-Ming HUANG, Lai TU, Chih-Hsun CHOU
  • Publication number: 20110090608
    Abstract: An electrical-overstress (EOS) protection circuit for an electronic device includes series-connected resistors, a mode-control switch, and a bias circuit. The series-connected resistors are electrically coupled between an input and an output, and the mode-control switch is electrically coupled between the output and a ground. The bias circuit is electrically coupled to the input for generating a mode-control signal to control the mode-control switch. The bias circuit generates the mode-control signal in a way such that the mode-control switch is open in a normal mode and closed in an EOS mode.
    Type: Application
    Filed: February 23, 2010
    Publication date: April 21, 2011
    Applicant: HIMAX TECHNOLOGIES LIMITED
    Inventors: CHUNG-MING HUANG, TIEH-YEN CHANG, HUNG-SUI LIN
  • Patent number: 7902600
    Abstract: A metal oxide semiconductor device comprising a substrate, at least an isolation structure, a deep N-type well, a P-type well, a gate, a plurality of N-type extension regions, an N-type drain region, an N-type source region and a P-type doped region is provided. The N-type extension regions are disposed in the substrate between the isolation structures and either side of the gate, while the N-type drain region and the N-type source region are respectively disposed in the N-type extension regions at both sides of the gate. The P-type well surrounds the N-type extension regions, and the P-type doped region is disposed in the P-type well of the substrate and is isolated from the N-type source region by the isolation structure.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: March 8, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Shin-Kuang Lin, Lung-Chih Wang, Chung-Ming Huang, Che-Ching Yang, Chun-Ming Chen
  • Patent number: 7894367
    Abstract: Presented are methods and systems for providing bandwidth estimation and correction in a communications network. Bandwidth estimation and correction can include calculating a round trip time (RTT) value and a packet loss rate (PLR) value for each packet of a set of packets transmitted at different points in time from a server to a client terminal over the communications network; determining a bandwidth estimate based on the RTT and PLR values for the set of packets transmitted; determining a bandwidth measurement based on the RTT and PLR values for the set of packets; and determining a corrected bandwidth estimate based on the bandwidth estimate and the bandwidth measurement.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: February 22, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Chung-Wei Lin, Xin-Ying Lin, Chung-Ming Huang
  • Publication number: 20100229019
    Abstract: A method of controlling spread-spectrum clock generation is disclosed. A first-in first-out (FIFO) buffer is first monitored. When the FIFO buffer is determined to be abnormal, an associated spread-spectrum clock generator (SSCG) is turned off or its spread range is decreased.
    Type: Application
    Filed: March 3, 2009
    Publication date: September 9, 2010
    Inventors: Chung-Ming Huang, Kuo-Chan Huang
  • Publication number: 20100148250
    Abstract: A metal oxide semiconductor device comprising a substrate, at least an isolation structure, a deep N-type well, a P-type well, a gate, a plurality of N-type extension regions, an N-type drain region, an N-type source region and a P-type doped region is provided. The N-type extension regions are disposed in the substrate between the isolation structures and either side of the gate, while the N-type drain region and the N-type source region are respectively disposed in the N-type extension regions at both sides of the gate. The P-type well surrounds the N-type extension regions, and the P-type doped region is disposed in the P-type well of the substrate and is isolated from the N-type source region by the isolation structure.
    Type: Application
    Filed: December 11, 2008
    Publication date: June 17, 2010
    Applicant: United Microelectronics Corp.
    Inventors: Shin-Kuang Lin, Lung-Chih Wang, Chung-Ming Huang, Che-Ching Yang, Chun-Ming Chen
  • Publication number: 20100145618
    Abstract: Vehicle collision management systems and methods for use in a first vehicle are provided. The system includes an information collection unit, an information filter, and a collision calculation unit. The information collection unit receives driving data corresponding to a second vehicle, wherein the driving data includes a position of the second vehicle, and a driving course and a velocity of the second vehicle. The information filter filters the driving data of the second vehicle according to the driving data of the second vehicle and the first vehicle. The collision calculation unit performs a collision management for the first vehicle according to the filtered driving data of the second vehicle and the first vehicle.
    Type: Application
    Filed: December 29, 2008
    Publication date: June 10, 2010
    Applicant: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Shih-Yang Lin, Chung-Ming Huang, Chih-Hsun Chou
  • Patent number: 7597452
    Abstract: A lamp set with remotely group setting function comprising a plurality of lamp assemblies and a remote controller; each lamp assembly including a casing, a signal receiver; a lamp body, a base, a circuit assembly, a power device and a group switch set; the casing for receiving element of the lamp assembly; the function group switches having a plurality of buttons for selecting the package signals sent from the remote controller; the circuit assembly of the lamp assembly being electrically connected to the lamp body, the power device, the receiver, and the group switch set. The circuit assembly serving to read package signals received from the receiver; the group switch set determining whether it is necessary to process the received package signals; if necessary, the circuit assembly will send driving signals to the lamp body to has to present different light effects according to the signals.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: October 6, 2009
    Assignee: Avertronics Inc.
    Inventors: Po-Wen Jeng, Chung-Ming Huang, Yuan-Sheng Liang, Liang-Chia Tseng
  • Publication number: 20090212864
    Abstract: A preamplifier used in a receiver is provided. The preamplifier comprises an input circuit and an output circuit. The input circuit receives an input differential voltage pair, pulls it down when the common voltage of the input differential voltage pair is higher than a reference voltage. The output circuit receives the input differential voltage pair outputted from the input circuit to pull high or low an output voltage accordingly.
    Type: Application
    Filed: February 21, 2008
    Publication date: August 27, 2009
    Applicant: HIMAX TECHNOLOGIES LIMITED
    Inventors: Chih-Haur Huang, Chung-Ming Huang