Abstract: Peptide sequencing is important in decoding data stored in a data-encoded peptide. Tandem mass spectrometry (MS/MS) is particularly useful for peptide sequencing. In a computer-implemented method for sequencing the data-encoded peptide from an experimental spectrum, raw data of the experimental spectrum are first preprocessed to remove uninterpretable peaks to yield preprocessed data. A first set of one or more candidate sequences contending for a peptide sequence of the peptide is identified from a spectrum graph. The spectrum graph is formed according to the preprocessed data rather than the raw data for generating a fewer number of candidate sequences to thereby reduce a time cost in sequencing. The first candidate-sequence set is then processed to estimate the peptide sequence to thereby obtain a set of peptide-sequence estimate(s). Each estimate is verified whether it is invalid. The set of peptide-sequence estimate(s) is purged to remove any invalid estimate.

Abstract: Methods and systems for storing digital data into peptide sequences and retrieving digital data from peptide sequences are disclosed. The method for storing digital data into peptide sequences may include: encoding the digital data into a digital code; translating the digital code into the peptide sequences; and synthesizing the translated peptide sequences. The method for retrieving digital data from peptide sequences may include: sequencing and determining an order of the peptide sequences; converting the peptide sequences with the determined order into a digital code; and decoding the digital data from the digital code. Codes with error-correction capability are developed for encoding digital data into peptide sequences, and a computational method implemented in a software is developed for sequencing the digital data bearing peptides.

Abstract: Methods and systems for storing digital data into peptide sequences and retrieving digital data from peptide sequences are disclosed. The method for storing digital data into peptide sequences may include: encoding the digital data into a digital code; translating the digital code into the peptide sequences; and synthesizing the translated peptide sequences. The method for retrieving digital data from peptide sequences may include: sequencing and determining an order of the peptide sequences; converting the peptide sequences with the determined order into a digital code; and decoding the digital data from the digital code. Codes with error-correction capability are developed for encoding digital data into peptide sequences, and a computational method implemented in a software is developed for sequencing the digital data bearing peptides.

Abstract: This invention provides a cyclically-coupled (CC-) quasi-cyclic (QC-) low-density parity-check (LDPC) code and its decoder architecture. The essence of the invention is to introduce the convolutional nature to a plurality of individual block codes internally so as to form a resultant block code with a prolonged code length while slightly increasing the hardware complexity in decoder realization. The CC-QC-LDPC code is formed by cyclically coupling a plurality of sub-codes each being a QC-LDPC code such that overlapping of some variable nodes between two consecutive sub-codes results. The decoder comprises plural sub-decoders each configured to decode the channel messages for one sub-code. The sub-decoders are arranged in a ring shape such that an individual sub-decoder is configured to communicate edge messages with two neighboring sub-decoders adjacent to said individual sub-decoder in the decoding of the channel messages.

Abstract: This invention provides a cyclically-coupled (CC-) quasi-cyclic (QC-) low-density parity-check (LDPC) code and its decoder architecture. The essence of the invention is to introduce the convolutional nature to a plurality of individual block codes internally so as to form a resultant block code with a prolonged code length while slightly increasing the hardware complexity in decoder realization. The CC-QC-LDPC code is formed by cyclically coupling a plurality of sub-codes each being a QC-LDPC code such that overlapping of some variable nodes between two consecutive sub-codes results. The decoder comprises plural sub-decoders each configured to decode the channel messages for one sub-code. The sub-decoders are arranged in a ring shape such that an individual sub-decoder is configured to communicate edge messages with two neighboring sub-decoders adjacent to said individual sub-decoder in the decoding of the channel messages.

Abstract: A Low-Density Parity-Check Convolutional Code (LPDCCC) decoder (10) for partial parallel decoding of low-density parity-check convolutional codes, the decoder having: a plurality of pipeline processors (11) to receive channel messages and edge-messages; each processor (11) having: a plurality of block processing units (BPUs) (13), each BPU (13) having a plurality of check node processors (CNPs) (14) to process check nodes that enter into the processor (11) and a plurality of variable node processors (VNPs) (15) to process variable nodes that are about to leave the processor (11); and a plurality of Random Access Memory (RAM) blocks (30) for dynamic message storage of the channel messages and the edge-messages; wherein in each processor (11), the VNPs (15) are directly connected to corresponding RAM blocks (30), and the CNPs (14) are directly connected to corresponding RAM blocks (30) such that the connections from the VNPs (15) and CNPs (14) to the corresponding RAM blocks (30) are pre-defined and fixed accor

Abstract: A Low-Density Parity-Check Convolutional Code (LPDCCC) decoder (10) for partial parallel decoding of low-density parity-check convolutional codes, the decoder comprising: a plurality of pipeline processors (11) to receive channel messages and edge-messages; each processor (11) having: a plurality of block processing units (BPUs) (13), each BPU (13) having a plurality of check node processors (CNPs) (14) to process check nodes that enter into the processor (11) and a plurality of variable node processors (VNPs) (15) to process variable nodes that are about to leave the processor (11); and a plurality of Random Access Memory (RAM) blocks (30) for dynamic message storage of the channel messages and the edge-messages; wherein in each processor (11), the VNPs (15) are directly connected to corresponding RAM blocks (30), and the CNPs (14) are directly connected to corresponding RAM blocks (30) such that the connections from the VNPs (15) and CNPs (14) to the corresponding RAM blocks (30) are pre-defined and fixed a

Abstract: An approximated lower-triangle structure for the parity-check matrix of low-density parity-check (LDPC) codes which allows linear-time-encoding complexity of the codes is disclosed, and the parity part of the parity-check matrix is semi-deterministic which allows high flexibility when designing the LDPC codes in order to provide higher error-correction capabilities than a typical dual-diagonal structure.

Abstract: A method for encoding data, the method comprising: creating m parity bits from k data bits based on a parity-check matrix (40), the parity-check matrix (40) including a data portion (41) and a parity portion (42), the parity portion (42) includes sub-block matrices, each sub-block matrix being any one from the group consisting of: zero matrix, identity matrix and permutation matrix; and forming a codeword containing the k data bits and the created m parity bits; wherein an upper diagonal is defined in the parity portion (42) starting from the first sub-block matrix in the second column extending to the second last sub-block matrix in the last column, and each sub-block matrix on the upper diagonal is an identity matrix or a permutation matrix, and the sub-block matrices (44) above the upper diagonal are zero matrices; each column from the second column to the third last column of the parity portion (42) contains one or more identity matrices or permutation matrices below the upper diagonal (45) and the remain

Abstract: Digital communication schemes using chaotic signals as carriers can be broadly classified into two categories. In the first category, the chaotic signals carrying the information have to be synchronously regenerated at the receiver, which may be applicable to low noise environment. The second category requires no synchronous regeneration of the carrying chaotic signals in the receiver. An example of the second category utilizes a specific bit structure, which may not be able to resist unintended reception because the fabricated bit structure can be relatively easily detected. This invention involves systems and methods for transmitting digital messages modulated as chaotic signals, and the demodulation methods. One individual chaotic signal generator having a specific chaotic characteristic value is responsible for generating a chaotic signal for each possible value of the digital message according to a chaotic algorithm.

Abstract: A digital communication system based on the use of chaotic carriers is disclosed. For each symbol to be sent, the transmitter sends a reference chaotic signal followed by a transformed version of the reference chaotic signal. For different symbols, different transformations are performed. Also, the transformations are designed such that the transformed versions of the reference chaotic signal do not resemble the original reference chaotic signal. As a consequence, little information can be deduced by inspecting the frequency spectrum of the transmitted signal. Moreover, even if the communication could be detected, it is difficult to decode the messages because there are numerous transformations possible.

Abstract: A digital communication system based on the use of chaotic carriers is disclosed. For each symbol to be sent, the transmitter sends a reference chaotic signal followed by a transformed version of the reference chaotic signal. For different symbols, different transformations are performed. Also, the transformations are designed such that the transformed versions of the reference chaotic signal do not resemble the original reference chaotic signal. As a consequence, little information can be deduced by inspecting the frequency spectrum of the transmitted signal. Moreover, even if the communication could be detected, it is difficult to decode the messages because there are numerous transformations possible.

Abstract: Digital communication schemes using chaotic signals as carriers can be broadly classified into two categories. In the first category, the chaotic signals carrying the information have to be synchronously regenerated at the receiver, which may be applicable to low noise environment. The second category requires no synchronous regeneration of the carrying chaotic signals in the receiver. An example of the second category utilizes a specific bit structure, which may not be able to resist unintended reception because the fabricated bit structure can be relatively easily detected. This invention involves systems and methods for transmitting digital messages modulated as chaotic signals, and the demodulation methods. One individual chaotic signal generator having a specific chaotic characteristic value is responsible for generating a chaotic signal for each possible value of the digital message according to a chaotic algorithm.