Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.

Abstract: A microelectromechanical system (MEMS) structure and method of forming the MEMS device, including forming a first metallization structure over a complementary metal-oxide-semiconductor (CMOS) wafer, where the first metallization structure includes a first sacrificial oxide layer and a first metal contact pad. A second metallization structure is formed over a MEMS wafer, where the second metallization structure includes a second sacrificial oxide layer and a second metal contact pad. The first metallization structure and second metallization structure are then bonded together. After the first metallization structure and second metallization structure are bonded together, patterning and etching the MEMS wafer to form a MEMS element over the second sacrificial oxide layer. After the MEMS element is formed, removing the first sacrificial oxide layer and second sacrificial oxide layer to allow the MEMS element to move freely about an axis.

Abstract: Some implementations described herein include systems and techniques for fabricating a wafer-on-wafer product using a filled lateral gap between beveled regions of wafers included in a stacked-wafer assembly and along a perimeter region of the stacked-wafer assembly. The systems and techniques include a deposition tool having an electrode with a protrusion that enhances an electromagnetic field along the perimeter region of the stacked-wafer assembly during a deposition operation performed by the deposition tool. Relative to an electromagnetic field generated by a deposition tool not including the electrode with the protrusion, the enhanced electromagnetic field improves the deposition operation so that a supporting fill material may be sufficiently deposited.

Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.

Abstract: Provided are a transistor structure and a method of forming the same. The transistor structure includes a gate electrode; a gate dielectric layer, disposed on the gate electrode; an active layer, disposed on the gate dielectric layer; a pair of source/drain (S/D) features, disposed on the active layer; and an isolation structure, laterally surrounding the pair of S/D features, wherein the isolation structure at least comprises a blocking layer and an upper dielectric layer on the blocking layer.

Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.

Abstract: A memory device includes a main array comprising main memory cells; a redundancy array comprising redundancy memory cells; and write circuitry configured to perform a first programming operation on a main memory cell, to detect whether a current of the main memory cell exceeds a predefined current threshold during the first programming operation, and to disable a second programming operation for a redundancy memory cell if the current of the main memory cell exceeds the predefined current threshold during the first programming operation.

Abstract: A stacked aluminum electrolytic capacitor includes a lead frame, a capacitor set, and at least one laser welding area. The lead frame includes a positive electrode end and a negative electrode end spaced from the positive electrode end. The capacitor set includes a plurality of stacked capacitor elements each having a positive electrode portion electrically connected to the positive electrode end and a negative electrode portion electrically connected to the negative electrode end. The at least one laser welding area is configured by a laser source capable of emitting a laser beam to perform laser welding on the positive electrode end and the positive electrode portion to form a fusion connection therebetween.

Abstract: A stacked aluminum electrolytic capacitor includes a lead frame, a capacitor set, and at least one laser welding area. The lead frame includes a positive electrode end and a negative electrode end spaced from the positive electrode end. The capacitor set includes a plurality of stacked capacitor elements each having a positive electrode portion electrically connected to the positive electrode end and a negative electrode portion electrically connected to the negative electrode end. The at least one laser welding area is configured by a laser source capable of emitting a laser beam to perform laser welding on the positive electrode end and the positive electrode portion to form a fusion connection therebetween.

Abstract: An electrolytic capacitor includes a core package formed by stacking and rolling an anode foil, a cathode foil, a plurality of paper spacers, and two terminal leads. The core package includes a solid electrolyte layer. The solid electrolyte layer is impregnated with an electrolytic solution. The electrolytic solution includes an ester compound and a sulfone compound. A content of the ester compound is more than 30% by mass. A content of the sulfone compound is more than 40% by mass. The sum of the contents of the ester compound and the sulfone compound is larger than 90% by mass. Thus, an electrolytic capacitor with excellent reliability is provided.

Abstract: An electrolytic capacitor includes a body having a casing and a capacitor core. The casing includes a side having an opening intercommunicated with a receiving space of the casing in which the capacitor core is mounted. The sealing cover is mounted in the opening and includes a lid and an enveloping member. The lid includes a first side adjacent to the capacitor core, a second side, and an outer periphery extending between the first side and the second side of the lid. The enveloping member is securely engaged with the lid by insert molding. The enveloping member is engaged with the first side, the second side, and the outer periphery of the lid.

Abstract: The present disclosure relates to a semiconductor substrate, a semiconductor package structure, and methods for making the same. A method includes providing a substrate and a carrier layer. The substrate includes a first patterned metal layer, a second patterned metal layer spaced from the first patterned metal layer, and a dielectric layer disposed between the first patterned metal layer and the second patterned metal layer. The dielectric layer covers the second patterned metal layer. The dielectric layer defines first openings exposing the second patterned metal layer, and further defines a via opening extending from the first patterned metal layer to the second patterned metal layer. A conductive material is disposed in the via and electrically connects the first patterned metal layer to the second patterned metal layer. The carrier layer defines second openings exposing the second patterned metal layer.

Abstract: The present disclosure relates to a semiconductor substrate, a semiconductor package structure, and methods for making the same. A method includes providing a substrate and a carrier layer. The substrate includes a first patterned metal layer, a second patterned metal layer spaced from the first patterned metal layer, and a dielectric layer disposed between the first patterned metal layer and the second patterned metal layer. The dielectric layer covers the second patterned metal layer. The dielectric layer defines first openings exposing the second patterned metal layer, and further defines a via opening extending from the first patterned metal layer to the second patterned metal layer. A conductive material is disposed in the via and electrically connects the first patterned metal layer to the second patterned metal layer. The carrier layer defines second openings exposing the second patterned metal layer.

Abstract: The present disclosure relates to a semiconductor substrate, a semiconductor package structure, and methods for making the same. A method includes providing a substrate and a carrier layer. The substrate includes a first patterned metal layer, a second patterned metal layer spaced from the first patterned metal layer, and a dielectric layer disposed between the first patterned metal layer and the second patterned metal layer. The dielectric layer covers the second patterned metal layer. The dielectric layer defines first openings exposing the second patterned metal layer, and further defines a via opening extending from the first patterned metal layer to the second patterned metal layer. A conductive material is disposed in the via and electrically connects the first patterned metal layer to the second patterned metal layer. The carrier layer defines second openings exposing the second patterned metal layer.

Abstract: The present disclosure relates to a semiconductor substrate, a semiconductor package structure, and methods for making the same. A method includes providing a substrate and a carrier layer. The substrate includes a first patterned metal layer, a second patterned metal layer spaced from the first patterned metal layer, and a dielectric layer disposed between the first patterned metal layer and the second patterned metal layer. The dielectric layer covers the second patterned metal layer. The dielectric layer defines first openings exposing the second patterned metal layer, and further defines a via opening extending from the first patterned metal layer to the second patterned metal layer. A conductive material is disposed in the via and electrically connects the first patterned metal layer to the second patterned metal layer. The carrier layer defines second openings exposing the second patterned metal layer.

Abstract: Computer based method for generation of a graph representation of a rule set for searching data transiting a network using a graph-based search model. A set of rules that describe strings or patterns of data to be identified in the data set, is expressed as a graph. As blocks of the data set are obtained for processing, the state of the graph is updated based upon the value of the received data block. The transition to the next state depends upon both the current state and the received data block. As blocks of data are received and processed, the graph is traversed until one of the rules is identified.

Abstract: Computer based method for generation of a graph representation of a rule set for searching data transiting a network using a graph-based search model. A set of rules that describe strings or patterns of data to be identified in the data set, is expressed as a graph. As blocks of the data set are obtained for processing, the state of the graph is updated based upon the value of the received data block. The transition to the next state depends upon both the current state and the received data block. As blocks of data are received and processed, the graph is traversed until one of the rules is identified.

Abstract: Computer based systems and methods for searching data transiting a network using a graph-based search model. A set of rules that describe strings or patterns of data to be identified in the data set, is expressed as a graph. As blocks of the data set are obtained for processing, the state of the graph is updated based upon the value of the received data block. The transition to the next state depends upon both the current state and the received data block. As blocks of data are received and processed, the graph is traversed until one of the rules is identified.

Abstract: Computer based systems and methods for searching data transiting a network using a graph-based search model. A set of rules that describe strings or patterns of data to be identified in the data set, is expressed as a graph. As blocks of the data set are obtained for processing, the state of the graph is updated based upon the value of the received data block. The transition to the next state depends upon both the current state and the received data block. As blocks of data are received and processed, the graph is traversed until one of the rules is identified.