Patents by Inventor Chung-Ming Yu

Chung-Ming Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250136682
    Abstract: Disclosed herein is generally directed to antibodies against the Siglec-3, and pharmaceutical compositions that comprise the antibodies. According to some embodiments of the present disclosure, the present anti-Siglec-3 antibodies may suppress the over activation of Siglec-3, thereby reversing the immunosuppression effects resulted therefrom. As such, the present antibodies may treat diseases associated with the over activation of Siglec-3, such as hepatitis B virus (HBV) infection, neurodegenerative diseases, autoimmune diseases, or cancers. Accordingly, the present disclosure also includes methods for the treatment and/or prophylaxis of the above diseases.
    Type: Application
    Filed: April 1, 2023
    Publication date: May 1, 2025
    Inventors: Shie-Liang HSIEH, Pei-Shan SUNG, An-Suei YANG, Chung-Ming YU
  • Publication number: 20250123458
    Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.
    Type: Application
    Filed: December 18, 2024
    Publication date: April 17, 2025
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
  • Patent number: 12278139
    Abstract: A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An epitaxial layer is formed on the sacrificial substrate. An etch stop layer is formed on the epitaxial layer. Carbon atoms are implanted into the etch stop layer. A capping layer and a device layer are formed on the etch stop layer. A handle substrate is bonded to the device layer. The sacrificial substrate, the epitaxial layer, and the etch stop layer having the carbon atoms are removed from the handle substrate.
    Type: Grant
    Filed: August 1, 2023
    Date of Patent: April 15, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Ming Chen, Kuei-Ming Chen, Po-Chun Liu, Chung-Yi Yu, Chia-Shiung Tsai
  • Patent number: 12274087
    Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: April 8, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Chih Lai, Shih-Min Chou, Nien-Ting Ho, Wei-Ming Hsiao, Li-Han Chen, Szu-Yao Yu, Chung-Yi Chiu
  • Publication number: 20250105137
    Abstract: Various embodiments of the present application are directed towards an integrated chip structure. The integrated chip structure includes a bottom electrode over a substrate, a top electrode over the bottom electrode, and a capacitor insulator structure between the bottom electrode and the top electrode. The capacitor insulator structure includes a first dielectric layer, a second dielectric layer over the first dielectric layer, and a third dielectric layer over the second dielectric layer. The first dielectric layer includes a first dielectric material. The second dielectric layer includes a second dielectric material that is different than the first dielectric material. The second dielectric material is an amorphous solid. The third dielectric layer includes the first dielectric material.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Inventors: Hsing-Lien Lin, Cheng-Te Lee, Rei-Lin Chu, Chii-Ming Wu, Yeur-Luen Tu, Chung-Yi Yu
  • Patent number: 12255104
    Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.
    Type: Grant
    Filed: August 2, 2023
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ching Lee, Hsin-Han Tsai, Shih-Hang Chiu, Tsung-Ta Tang, Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Da-Yuan Lee, Jian-Hao Chen, Chien-Hao Chen, Kuo-Feng Yu, Chia-Wei Chen, Chih-Yu Hsu
  • Publication number: 20250070013
    Abstract: A semiconductor package includes a redistribution structure, a supporting layer, a semiconductor device, and a transition waveguide structure. The redistribution structure includes a plurality of connectors. The supporting layer is formed over the redistribution structure and disposed beside and between the plurality of connectors. The semiconductor device is disposed on the supporting layer and bonded to the plurality of connectors, wherein the semiconductor device includes a device waveguide. The transition waveguide structure is disposed on the supporting layer adjacent to the semiconductor device, wherein the transition waveguide structure is optically coupled to the device waveguide.
    Type: Application
    Filed: November 14, 2024
    Publication date: February 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Hsiu-Jen Lin, Ming-Che Ho, Yu-Hsiang Hu, Chewn-Pu Jou, Cheng-Tse Tang
  • Publication number: 20250064620
    Abstract: A nasal dilator for treating breathing problem is provided, which includes a hollow nasal dilator body and a one-way flow resistance unit. The hollow nasal dilator body has a first end opening and a second end opening opposing the first end opening. The hollow nasal dilator body longitudinally extends from the first end opening to the second end opening and being adapted for insertion into a user's nostril with the second end opening placed within the user's nasal passage so that the hollow nasal dilator body supports and dilates the nasal passage. The one-way flow resistance unit is assembled to the hollow nasal dilator body and in proximity to the first end opening and away from the second end opening. The one-way flow resistance unit creates an exhalation flow resistance higher than an inhalation flow resistance such that an expiratory positive airway pressure is generated within the nasal passage.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 27, 2025
    Applicant: Somnics, Inc.
    Inventors: Chung-Chu CHEN, Chih-Jung LEE, Chieh-Neng YOUNG, Tung-Ming YU
  • Patent number: 12237418
    Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.
    Type: Grant
    Filed: August 4, 2023
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huan-Chieh Su, Chih-Hao Wang, Kuo-Cheng Chiang, Wei-Hao Wu, Zhi-Chang Lin, Jia-Ni Yu, Yu-Ming Lin, Chung-Wei Hsu
  • Publication number: 20250060542
    Abstract: A package includes an electronic die, a photonic die underlying and electronically communicating with the electronic die, a lens disposed on the electronic die, and a prism structure disposed on the lens and optically coupled to the photonic die. The prism structure includes first and second polymer layers, the first polymer layer includes a first curved surface concaving toward the photonic die, the second polymer layer embedded in the first polymer layer includes a second curved surface substantially conforming to the first curved surface, and an outer sidewall of the second polymer layer substantially aligned with an outer sidewall of the first polymer layer.
    Type: Application
    Filed: November 3, 2024
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Hsiang Hsu, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Chung-Ming Weng
  • Patent number: 12222545
    Abstract: An integrated circuit package and a method of forming the same are provided. The integrated circuit package includes a photonic integrated circuit die. The photonic integrated circuit die includes an optical coupler. The integrated circuit package further includes an encapsulant encapsulating the photonic integrated circuit die, a first redistribution structure over the photonic integrated circuit die and the encapsulant, and an opening extending through the first redistribution structure and exposing the optical coupler.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: February 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hsuan Tai, Chung-Ming Weng, Hung-Yi Kuo, Cheng-Chieh Hsieh, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 12210188
    Abstract: A semiconductor package includes a first die stack structure and a second die stack structure, an insulating encapsulation, a redistribution structure, at least one prism structure and at least one reflector. The first die stack structure and the second die stack structure are laterally spaced apart from each other along a first direction, and each of the first die stack structure and the second die stack structure comprises an electronic die; and a photonic die electronically communicating with the electronic die. The insulating encapsulation laterally encapsulates the first die stack structure and the second die stack structure. The redistribution structure is disposed on the first die stack structure, the second die stack structure and the insulating encapsulation, and electrically connected to the first die stack structure and the second die stack structure. The at least one prism structure is disposed within the redistribution structure and optically coupled to the photonic die.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Yi Kuo, Chen-Hua Yu, Cheng-Chieh Hsieh, Che-Hsiang Hsu, Chung-Ming Weng, Tsung-Yuan Yu
  • Patent number: 12210200
    Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.
    Type: Grant
    Filed: February 26, 2024
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
  • Patent number: 12116407
    Abstract: Provided herein is a method for treating neurodegenerative diseases, such as Alzheimer's disease (AD), by use of monoclonal antibody, which exhibits a binding affinity to Siglec-3 receptor. According to some embodiments of the present disclosure, the monoclonal antibody is capable of enhancing phagocytosis of neurotoxic peptides by immune cells thereby providing a neuroprotective effect to a subject in need thereof.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: October 15, 2024
    Assignee: Academia Sinica
    Inventors: Shie-Liang Hsieh, Pei-Shan Sung, Ming-Ting Huang, An-Suei Yang, Chung-Ming Yu
  • Patent number: 12103969
    Abstract: Disclosed herein is a novel monoclonal antibody exhibiting binding affinity to Siglec-3 receptor. According to the embodiment, the monoclonal antibody is capable of reversing HBV-induced immunosuppression. Accordingly, also disclosed herein are the uses thereof in the treatment and/or prophylaxis of hepatitis B virus (HBV) infection.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: October 1, 2024
    Assignee: Academia Sinica
    Inventors: Shie-Liang Hsieh, Tsung-Yu Tsai, An-Suei Yang, Chung-Ming Yu, Cheng-Yuan Peng
  • Publication number: 20240277865
    Abstract: Disclosed herein is a phage-displayed single-chain variable fragment (scFv) library, which comprises a plurality of phage-displayed scFvs characterized with a specific sequence in each CDR. The present phage-displayed scFv library is useful in selecting an antibody fragment exhibiting a binding affinity and specificity to mesothelin (MSLN). Also disclosed herein are a recombinant antibody specific to MSLN, an immunoconjugate comprising the recombinant antibody, and uses thereof in treating cancers.
    Type: Application
    Filed: June 8, 2022
    Publication date: August 22, 2024
    Inventors: An-Suei YANG, Hung-Ju HSU, Chao-Ping TUNG, Chung-Ming YU, Chi-Yung CHEN, Hong-Sen CHEN, Yu-Chuan HUANG, Pei-Hsun TSAI, Szu-Yu LIN, Hung-Pin PENG
  • Publication number: 20230212554
    Abstract: Disclosed herein are methods for selecting an antibody fragment specific to an influenza virus. According to certain embodiments of the present disclosure, the influenza virus may be influenza virus type A (IAV) or influenza virus type B (IBV). Also disclosed herein are the selected antibodies, recombinant antibody produced from the selected antibodies, and the uses thereof in the diagnosis of influenza virus infection.
    Type: Application
    Filed: June 7, 2021
    Publication date: July 6, 2023
    Applicant: Academia Sinica
    Inventors: An-Suei YANG, Chung-Ming YU, Ing-Chien CHEN, Chao-Ping TUNG, Hung-Pin PENG
  • Publication number: 20230168249
    Abstract: Disclosed herein are recombinant antibodies or the fragment thereof for detecting severe acute respiratory syndrome coronavirus (SARS-CoV). According to some embodiments, the SARS-CoV is SARS-CoV-1. According to some alternative embodiments, the SARS-CoV is SARS-CoV-2. Also disclosed herein are a kit comprising the recombinant antibodies, and a method for diagnosing the infection of SARS-CoV by using the recombinant antibody or the kit.
    Type: Application
    Filed: May 4, 2021
    Publication date: June 1, 2023
    Applicant: Academia Sinica
    Inventors: An-Suei YANG, Chao-Ping TUNG, Chung-Ming YU, Chi-Yung CHEN, Yu-Chuan HUANG, Pei-Hsun TSAI, Szu-Yu LIN, Hung-Ju HSU, Hung-Pin PENG, Fei-Hung HUNG
  • Patent number: 11434277
    Abstract: Disclosed herein are methods for high-throughput screening of a virus-specific neutralizing antibody. According to certain embodiments of the present disclosure, the virus is an influenza virus. Also disclosed herein are the antibodies selected by the high-throughput screening method, and the uses thereof in the prophylaxis and/or treatment of viral infection.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: September 6, 2022
    Assignee: ACADEMIA SINICA
    Inventors: An-Suei Yang, Ing-Chien Chen, Yi-Kai Chiu, Chung-Ming Yu, Cheng-Chung Lee, Chao-Ping Tung, Yueh-Liang Tsou, Yi-Jen Huang, Chia-Lung Lin, Hong-Sen Chen, Hwei-Jiung Wang
  • Publication number: 20220213188
    Abstract: Provided herein is a method for treating neurodegenerative diseases, such as Alzheimer's disease (AD), by use of monoclonal antibody, which exhibits a binding affinity to Siglec-3 receptor. According to some embodiments of the present disclosure, the monoclonal antibody is capable of enhancing phagocytosis of neurotoxic peptides by immune cells thereby providing a neuroprotective effect to a subject in need thereof.
    Type: Application
    Filed: September 25, 2019
    Publication date: July 7, 2022
    Applicant: Academia Sinica
    Inventors: Shie-Liang HSIEH, Pei-Shan SUNG, Ming-Ting HUANG, An-Suei YANG, Chung-Ming YU