Abstract: A structure of a printed circuit board and a carrier is coupled with a chip, and the printed circuit board contains: a trace, and a dielectric layer. The carrier includes at least an element. The trace at least includes a terminal; the trace has an upper surface, a lower surface, and a side edge, the dielectric layer includes a predetermined opening, an upper surface, a lower surface, and a side edge, wherein the predetermined opening is formed by a portion of the dielectric layer and corresponds to the terminal of the trace. And the carrier is coupled with the dielectric layer.

Abstract: A printed circuit board contains: a first insulator including an upper surface, a lower surface, and a blind via passing through the first insulator; a first trace including an upper surface, a lower surface, a first side edge, and a terminal on the lower surface of the first trace; and a first conductive pad including an upper surface, a lower surface, a side edge, and an opening passing through the first conductive pad. The first trace is connected with the upper surface of the first insulator. The terminal correspondingly exposes inside the blind via of the first insulator. The side edge and the lower surface of the first conductive pad are connected with the first insulator, the upper surface of the first conductive pad exposes outside the lower surface of the first insulator, and the opening of the first conductive pad corresponds to the terminal of the first trace.

Abstract: A printing circuit board includes: an insulator having an upper surface, a lower surface and an opening formed in the lower surface, and a trace having an upper surface, a lower surface and a side edge and received in said insulator. The upper surface of said trace is exposed out of the insulator and a portion of the lower surface of said trace is exposed by said opening for external connection.

Abstract: A printed circuit board at least includes an insulator with a predetermined blind via area which may become a blind via which is penetrated through said insulator through a process of drilling. A portion of a conductive material may be filled therein to allow both the trace on the upper surface of the insulator and/or the conductive pad on the lower surface of insulator to be electrically connected. The quantity of the trace is increased. The blind via may also have a vent so that the gas sealed in the blind via enables to be released to the atmosphere promptly through the vent while heating.

Abstract: A Printing Circuit Board is disclosed, a preferred embodiment in accordance with the present invention includes: an insulator, and a trace(s) which is embedded therein, wherein both the upper surface and a portion of the lower surface of said trace exposed out of said insulator, nevertheless, another portion of the lower surface of trace encapsulated by said insulator, in this manner, it is not necessary for said lower surface of trace to be coupled with a solder mask which is for protecting said lower surface of trace, as this result, the advantages of said PCB includes: (1). The cost is saved; (2). The thickness is thinner; and (3). the reliability of said PCB is enhanced.

Abstract: A multichip stacking structure is provided, including a chip carrier; a plurality of semiconductor chips stacked on the chip carrier in a stepped manner that an overlying chip mounted on an underlying chip of the plurality of semiconductor chips has a suspended portion free of being in contact with the underlying chip; and a bump mounted on the chip carrier at a position corresponding to a suspended side of the stacked semiconductor chips where the suspended portion of the overlying chip is located. The bump can serve as a blocking member or a filling member to prevent the semiconductor chips from delamination or formation of voids during a molding process.

Abstract: A method for fabricating a semiconductor device installed with passive components is provided.

Abstract: A multi-chip semiconductor package and a method for fabricating the same are disclosed. The method includes electrically connecting a first chip mounted onto a substrate with the substrate through a plurality of first bonding wires; applying an adhesive layer on the substrate at a position proximate to the first chip in a horizontal direction, wherein the adhesive layer at least covers a portion of wireloop of each of the first bonding wires and a first bonding region bonded thereto, such that a second chip overlaps the first bonding region to reduce space wasted on the substrate, thereby allowing more and larger-sized chips to be attached thereon.

Abstract: The present invention provides an insertion-type semiconductor device and a fabrication method thereof, including the steps of: mounting a chip on a BGA substrate and performing a packaging molding process; providing an electrical connecting board formed with a plurality of electrical terminals thereon for allowing the packaged substrate to electrically connect with the electrical terminals on the electrical connecting board via a conductive element thereof; covering a lid to form an insertion-type semiconductor device. As size of the solder pads is much smaller than the electrical terminals of the insertion-type semiconductor device, the area under the semiconductor chip can be reduced to minimize the deformable area of the semiconductor chip when being pressed in the molding process, thereby preventing damage to the semiconductor chip and also meeting the specification requirement of an insertion-type semiconductor device.

Abstract: A multi-chip stack structure includes a chip carrier, a plurality of chips stacked stepwise on the chip carrier, and a passive component disposed on the chip carrier. The passive component is located under the stepwise chips that are cantilevered over it. Therefore, the passive component serves as a block element or a filling element in the molding process, and problems such as chip peeling void are prevented. Meanwhile, the electrical properties of the package are improved.

Abstract: A circuit board and a package structure thereof are proposed. The circuit board includes a main body and a solder mask layer covered on a surface of the main body. The circuit board is formed with a cutting path to define a plurality of array-arranged circuit board units, wherein the solder mask layer is formed with a groove at a position corresponding to the cutting path to expose the main body of the circuit board. By such arrangement, when a laser is employed to perform a singulation process after a chip mounting process and a packaging process have been completed on the circuit board unit, the problem wherein the solder mask layer melts on the cutting path of the circuit board due to a thermal effect caused by the laser is avoided, so as to avoid the generation of irregular and uneven surface of the cutting plane. Additionally, chippings on a surface of a substrate can be prevented from being generated, so as to avoid contamination of subsequent processes.

Abstract: A multichip stacking structure is provided, including a chip carrier; a plurality of semiconductor chips stacked on the chip carrier in a stepped manner that an overlying chip mounted on an underlying chip of the plurality of semiconductor chips has a suspended portion free of being in contact with the underlying chip; and a bump mounted on the chip carrier at a position corresponding to a suspended side of the stacked semiconductor chips where the suspended portion of the overlying chip is located. The bump can serve as a blocking member or a filling member to prevent the semiconductor chips from delamination or formation of voids during a molding process.

Abstract: A wire-bonded semiconductor device with an improved wire-arrangement scheme is proposed, which can help minimize abnormal wire sweep during encapsulation process. Among the bonding wires on the semiconductor device, those located in corners would be mostly susceptible to abnormal wire sweep, particularly a high-loop bonding wire that is located in immediate adjacency to a low-loop bonding wire located in one corner of the wire-bonded semiconductor device. To solve this problem, the low-loop bonding wire that is located in immediate adjacency to the sweep-susceptible high-loop bonding wire is erected substantially to the same loop height as the high-loop bonding wire, so that it can serve as a shield to the sweep-susceptible high-loop bonding wire against the flow of injected resin during encapsulation process, thus preventing abnormal wire sweep.