Patents by Inventor Chung-Pin CHOU
Chung-Pin CHOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11935722Abstract: This disclosure is directed to solutions of detecting and classifying wafer defects using machine learning techniques. The solutions take only one coarse resolution digital microscope image of a target wafer, and use machine learning techniques to process the coarse SEM image to review and classify a defect on the target wafer. Because only one coarse SEM image of the wafer is needed, the defect review and classification throughput and efficiency are improved. Further, the techniques are not distractive and may be integrated with other defect detecting and classification techniques.Type: GrantFiled: July 21, 2022Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Pin Chou, Sheng-Wen Huang, Jun-Xiu Liu
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Publication number: 20230385502Abstract: A semiconductor wafer defect detection system captures test images of a semiconductor wafer. The system analyzes the test images with an analysis model trained with a machine learning process. The analysis model generates simulated integrated circuit layouts based on the test images. The system detects defects in the semiconductor wafer by comparing the simulated integrated circuit layouts to reference integrated circuit layouts.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Inventors: Chung-Pin CHOU, Chun-Wen WANG, Meng Ku CHI, Yan-Cheng CHEN, Jun-Xiu LIU
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Publication number: 20230384211Abstract: A process tube device can detect the presence of any external materials that may reside within a fluid flowing in the tube. The process tube device detects the external materials in-situ which obviates the need for a separate inspection device to inspect the surface of a wafer after applying fluid on the surface of the wafer. The process tube device utilizes at least two methods of detecting the presence of external materials. The first is the direct measurement method in which a light detecting sensor is used. The second is the indirect measurement method in which a sensor utilizing the principles of Doppler shift is used. Here, contrary to the first method that at least partially used reflected or refracted light, the second method uses a Doppler shift sensor to detect the presence of the external material by measuring the velocity of the fluid flowing in the tube.Type: ApplicationFiled: July 28, 2023Publication date: November 30, 2023Inventors: Yu-Jen YANG, Chung-Pin CHOU, Yan-Cheng CHEN, Kai-Lin Chuang, Jun-Xiu Liu, Sheng-Ching Kao
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Publication number: 20230369092Abstract: Some implementations described herein provide techniques and apparatuses for a semiconductor processing tool including an electrostatic chuck having a voltage-regulation system to regulate an electrical potential throughout regions of a semiconductor substrate positioned above the electrostatic chuck. The voltage-regulation system may determine that an electrical potential within a region of the semiconductor substrate does not satisfy a threshold. The voltage-regulation system may, based on determining that the electrical potential throughout the region does not satisfy the threshold, position one or more electrically-conductive pins within the region. While positioned within the region, the one or more electrically-conductive pins may change the electrical potential of the region.Type: ApplicationFiled: July 26, 2023Publication date: November 16, 2023Inventors: Chung-Pin CHOU, Kai-Lin CHUANG, Sheng-Wen HUANG, Yan-Cheng CHEN, Jun Xiu LIU
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Patent number: 11816411Abstract: A semiconductor wafer defect detection system captures test images of a semiconductor wafer. The system analyzes the test images with an analysis model trained with a machine learning process. The analysis model generates simulated integrated circuit layouts based on the test images. The system detects defects in the semiconductor wafer by comparing the simulated integrated circuit layouts to reference integrated circuit layouts.Type: GrantFiled: November 24, 2020Date of Patent: November 14, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Pin Chou, Chun-Wen Wang, Meng Ku Chi, Yan-Cheng Chen, Jun-Xiu Liu
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Publication number: 20230360975Abstract: In a method of inspection of a semiconductor substrate a first beam of light is split into two or more second beams of light. The two or more second beams of light are respectively transmitted onto a first set of two or more first locations on top of the semiconductor substrate. In response to the transmitted two or more second beams of light, two or more reflected beams of light from the first set of two or more first locations are received. The received two or more reflected beams of light are detected to generate two or more detected signals. The two or more detected signals are analyzed to determine whether a defect exists at the set of the two or more first locations.Type: ApplicationFiled: July 18, 2023Publication date: November 9, 2023Inventors: Sheng He HUANG, Chung-Pin CHOU, Shiue-Ming GUO, Hsuan-Chia KAO, Yan-Cheng CHEN, Sheng-Ching KAO, Jun Xiu LIU
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Patent number: 11764094Abstract: Some implementations described herein provide techniques and apparatuses for a semiconductor processing tool including an electrostatic chuck having a voltage-regulation system to regulate an electrical potential throughout regions of a semiconductor substrate positioned above the electrostatic chuck. The voltage-regulation system may determine that an electrical potential within a region of the semiconductor substrate does not satisfy a threshold. The voltage-regulation system may, based on determining that the electrical potential throughout the region does not satisfy the threshold, position one or more electrically-conductive pins within the region. While positioned within the region, the one or more electrically-conductive pins may change the electrical potential of the region.Type: GrantFiled: February 18, 2022Date of Patent: September 19, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Pin Chou, Kai-Lin Chuang, Sheng-Wen Huang, Yan-Cheng Chen, Jun Xiu Liu
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Patent number: 11749571Abstract: In a method of inspection of a semiconductor substrate a first beam of light is split into two or more second beams of light. The two or more second beams of light are respectively transmitted onto a first set of two or more first locations on top of the semiconductor substrate. In response to the transmitted two or more second beams of light, two or more reflected beams of light from the first set of two or more first locations are received. The received two or more reflected beams of light are detected to generate two or more detected signals. The two or more detected signals are analyzed to determine whether a defect exists at the set of the two or more first locations.Type: GrantFiled: August 31, 2021Date of Patent: September 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sheng He Huang, Chung-Pin Chou, Shiue-Ming Guo, Hsuan-Chia Kao, Yan-Cheng Chen, Sheng-Ching Kao, Jun Xiu Liu
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Publication number: 20230268215Abstract: Some implementations described herein provide techniques and apparatuses for a semiconductor processing tool including an electrostatic chuck having a voltage-regulation system to regulate an electrical potential throughout regions of a semiconductor substrate positioned above the electrostatic chuck. The voltage-regulation system may determine that an electrical potential within a region of the semiconductor substrate does not satisfy a threshold. The voltage-regulation system may, based on determining that the electrical potential throughout the region does not satisfy the threshold, position one or more electrically-conductive pins within the region. While positioned within the region, the one or more electrically-conductive pins may change the electrical potential of the region.Type: ApplicationFiled: February 18, 2022Publication date: August 24, 2023Inventors: Chung-Pin CHOU, Kai-Lin CHUANG, Sheng-Wen HUANG, Yan-Cheng CHEN, Jun Xiu LIU
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Publication number: 20230060183Abstract: A process tube device can detect the presence of any external materials that may reside within a fluid flowing in the tube. The process tube device detects the external materials in-situ which obviates the need for a separate inspection device to inspect the surface of a wafer after applying fluid on the surface of the wafer. The process tube device utilizes at least two methods of detecting the presence of external materials. The first is the direct measurement method in which a light detecting sensor is used. The second is the indirect measurement method in which a sensor utilizing the principles of Doppler shift is used. Here, contrary to the first method that at least partially used reflected or refracted light, the second method uses a Doppler shift sensor to detect the presence of the external material by measuring the velocity of the fluid flowing in the tube.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: Yu-Jen YANG, Chung-Pin CHOU, Kai-Lin CHUANG, Yan-Cheng CHEN, Sheng-Ching KAO, Jun-Xiu LIU
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Publication number: 20230068133Abstract: In a method of inspection of a semiconductor substrate a first beam of light is split into two or more second beams of light. The two or more second beams of light are respectively transmitted onto a first set of two or more first locations on top of the semiconductor substrate. In response to the transmitted two or more second beams of light, two or more reflected beams of light from the first set of two or more first locations are received. The received two or more reflected beams of light are detected to generate two or more detected signals. The two or more detected signals are analyzed to determine whether a defect exists at the set of the two or more first locations.Type: ApplicationFiled: August 31, 2021Publication date: March 2, 2023Inventors: Sheng He HUANG, Chung-Pin CHOU, Shiue-Ming GUO, Hsuan-Chia KAO, Yan-Cheng CHEN, Sheng-Ching KAO, Jun Xiu LIU
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Publication number: 20220406632Abstract: An apparatus for inspecting a semiconductor substrate includes a rotatable base configured to support a substrate, and a nozzle arm includes a nozzle and a light monitoring device. The light monitoring device includes a laser transmitter and an array of light sensors arranged in the nozzle arm and facing the substrate. The light monitoring device is configured to transmit a laser pulse towards the substrate, wherein the laser pulse impinges on the substrate, receive a reflected laser pulse from the substrate, calculate whether one or more light sensors received the laser pulse, and calculate a distance between the light monitoring device and the substrate using the turnaround time for determining a process quality on the substrate.Type: ApplicationFiled: June 18, 2021Publication date: December 22, 2022Inventors: Chung-Pin CHOU, Kai-Lin CHUANG, Yan-Cheng CHEN, Jui Kuo LAI, Jun Xiu LIU
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Publication number: 20220359154Abstract: This disclosure is directed to solutions of detecting and classifying wafer defects using machine learning techniques. The solutions take only one coarse resolution digital microscope image of a target wafer, and use machine learning techniques to process the coarse SEM image to review and classify a defect on the target wafer. Because only one coarse SEM image of the wafer is needed, the defect review and classification throughput and efficiency are improved. Further, the techniques are not distractive and may be integrated with other defect detecting and classification techniques.Type: ApplicationFiled: July 21, 2022Publication date: November 10, 2022Inventors: Chung-Pin CHOU, Sheng-Wen HUANG, Jun-Xiu LIU
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Patent number: 11424101Abstract: This disclosure is directed to solutions of detecting and classifying wafer defects using machine learning techniques. The solutions take only one coarse resolution digital microscope image of a target wafer, and use machine learning techniques to process the coarse SEM image to review and classify a defect on the target wafer. Because only one coarse SEM image of the wafer is needed, the defect review and classification throughput and efficiency are improved. Further, the techniques are not distractive and may be integrated with other defect detecting and classification techniques.Type: GrantFiled: October 13, 2020Date of Patent: August 23, 2022Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Chung-Pin Chou, Sheng-Wen Huang, Jun-Xiu Liu
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Publication number: 20220236198Abstract: Wafer inspection apparatuses and methods are described. The wafer inspection apparatus includes an optical module, at least one wafer holder for carrying a plurality of wafers, and a plurality of optical sensors. The optical module is configured to emit a plurality of light beams for simultaneously scanning the plurality of wafers carried by the at least one wafer holder. The plurality of optical sensors is configured to receive the light beams reflected by the plurality of wafers.Type: ApplicationFiled: April 11, 2022Publication date: July 28, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chung-Pin Chou
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Patent number: 11300525Abstract: Wafer inspection apparatuses and methods are described. The wafer inspection apparatus includes an optical module, at least one wafer holder for carrying a plurality of wafers, and a plurality of optical sensors. The optical module is configured to emit a plurality of light beams for simultaneously scanning the plurality of wafers carried by the at least one wafer holder. The plurality of optical sensors is configured to receive the light beams reflected by the plurality of wafers.Type: GrantFiled: March 2, 2020Date of Patent: April 12, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chung-Pin Chou
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Publication number: 20210232745Abstract: A semiconductor wafer defect detection system captures test images of a semiconductor wafer. The system analyzes the test images with an analysis model trained with a machine learning process. The analysis model generates simulated integrated circuit layouts based on the test images. The system detects defects in the semiconductor wafer by comparing the simulated integrated circuit layouts to reference integrated circuit layouts.Type: ApplicationFiled: November 24, 2020Publication date: July 29, 2021Inventors: Chung-Pin CHOU, Chun-Wen WANG, Meng Ku CHI, Yan-Cheng CHEN, Jun-Xiu LIU
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Patent number: 11017522Abstract: A system includes an inspection device and an image processing unit. The inspection device is configured to scan a wafer to generate an inspected image. The image processing unit is configured to receive the inspected image, and is configured to analyze the inspected image by using at least one deep learning algorithm in order to determine whether there is any defect image shown in a region of interest in the inspected image. When there is at least one defect image shown in the region of interest in the inspected image, the inspection device is further configured to magnify the region of interest in the inspected image to generate a magnified inspected image for identification of defects.Type: GrantFiled: April 18, 2019Date of Patent: May 25, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Pin Chou, In-Tsang Lin, Sheng-Wen Huang, Yu-Ting Wang, Jui-Kuo Lai, Hsin-Hui Chou, Jun-Xiu Liu, Tien-Wen Wang
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Publication number: 20210033541Abstract: Wafer inspection apparatuses and methods are described. The wafer inspection apparatus includes an optical module, at least one wafer holder for carrying a plurality of wafers, and a plurality of optical sensors. The optical module is configured to emit a plurality of light beams for simultaneously scanning the plurality of wafers carried by the at least one wafer holder. The plurality of optical sensors is configured to receive the light beams reflected by the plurality of wafers.Type: ApplicationFiled: March 2, 2020Publication date: February 4, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Chung-Pin Chou
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Publication number: 20210027984Abstract: This disclosure is directed to solutions of detecting and classifying wafer defects using machine learning techniques. The solutions take only one coarse resolution digital microscope image of a target wafer, and use machine learning techniques to process the coarse SEM image to review and classify a defect on the target wafer. Because only one coarse SEM image of the wafer is needed, the defect review and classification throughput and efficiency are improved. Further, the techniques are not distractive and may be integrated with other defect detecting and classification techniques.Type: ApplicationFiled: October 13, 2020Publication date: January 28, 2021Inventors: Chung-Pin CHOU, Sheng-Wen HUANG, Jun-Xiu LIU