Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate having a base, a first fin, and a second fin over the base. The method includes forming a first trench in the base and between the first fin and the second fin. The method includes forming an isolation layer over the base and in the first trench. The first fin and the second fin are partially in the isolation layer. The method includes forming a first gate stack over the first fin and the isolation layer. The method includes forming a second gate stack over the second fin and the isolation layer. The method includes removing a bottom portion of the base. The isolation layer passes through the base after the bottom portion of the base is removed.

Abstract: A photo mask includes a plurality of device features, a first assist feature, and a second assist feature. The device features are in a patterning region of a device region. The first assist feature are in the patterning region and adjacent to the device features. The first assist feature is for correcting an optical proximity effect in a photolithography process. The second assist feature is in a non-patterning region of the device region. The second assist feature is a sub-resolution correction feature, and a first distance between the second assist feature and one of the device features closest to the second assist feature is greater than a second distance between adjacent two of the device features.

Abstract: This disclosure is directed to solutions of detecting and classifying wafer defects using machine learning techniques. The solutions take only one coarse resolution digital microscope image of a target wafer, and use machine learning techniques to process the coarse SEM image to review and classify a defect on the target wafer. Because only one coarse SEM image of the wafer is needed, the defect review and classification throughput and efficiency are improved. Further, the techniques are not distractive and may be integrated with other defect detecting and classification techniques.

Abstract: A device comprises a first transistor, a second transistor, a first contact, and a second contact. The first transistor comprises a first gate structure, first source/drain regions on opposite sides of the first gate structure, and first gate spacers spacing the first gate structure apart from the first source/drain regions. The second transistor comprises a second gate structure, second source/drain regions on opposite sides of the second gate structure, and second gate spacers spacing the second gate structure apart from the second source/drain regions. The first contact forms a first contact interface with one of the first source/drain regions. The second contact forms a second contact interface with one of the second source/drain regions. An area ratio of the first contact interface to top surface the first source/drain region is greater than an area ratio of the second contact interface to top surface of the second source/drain region.

Abstract: A device comprises a first transistor, a second transistor, a first contact, and a second contact. The first transistor comprises a first gate structure, first source/drain regions on opposite sides of the first gate structure, and first gate spacers spacing the first gate structure apart from the first source/drain regions. The second transistor comprises a second gate structure, second source/drain regions on opposite sides of the second gate structure, and second gate spacers spacing the second gate structure apart from the second source/drain regions. The first contact forms a first contact interface with one of the first source/drain regions. The second contact forms a second contact interface with one of the second source/drain regions. An area ratio of the first contact interface to top surface the first source/drain region is greater than an area ratio of the second contact interface to top surface of the second source/drain region.

Abstract: A device comprises a first transistor disposed within a first device region of a substrate and a second transistor disposed within a second device region of the substrate. The first transistor comprises first source/drain regions, a first gate structure laterally between the first source/drain regions, and first gate spacers respectively on opposite sidewalls of the first gate structure. The second transistor comprises second source/drain regions, a second gate structure laterally between the second source/drain regions, and second gate spacers respectively on opposite sidewalls of the second gate structure. The second source/drain regions of the second transistor have a maximal width greater than a maximal width of the first source/drain regions of the first transistor, but the second gate spacers of the second transistor have a thickness less than a thickness of the first gate spacers.

Abstract: A device comprises a first transistor disposed within a first device region of a substrate and a second transistor disposed within a second device region of the substrate. The first transistor comprises first source/drain regions, a first gate structure laterally between the first source/drain regions, and first gate spacers respectively on opposite sidewalls of the first gate structure. The second transistor comprises second source/drain regions, a second gate structure laterally between the second source/drain regions, and second gate spacers respectively on opposite sidewalls of the second gate structure. The second source/drain regions of the second transistor have a maximal width greater than a maximal width of the first source/drain regions of the first transistor, but the second gate spacers of the second transistor have a thickness less than a thickness of the first gate spacers.

Abstract: A method includes forming a first gate, a second gate, a third gate, and a fourth gate over a substrate, in which a first distance between the first gate and the second gate is less than a second distance between the third gate and the fourth gate. A first spacer over a sidewall of the first gate, a second spacer over a sidewall of the second gate, a third spacer over a sidewall of the third gate, and a fourth spacer over a sidewall of the fourth gate are formed. A mask layer over the first and second spacers is formed, in which the third and fourth spacers are exposed from the mask layer. The exposed third and fourth spacers are trimmed.

Abstract: A method for forming and setting a denture has the following steps: using a stereoscopic scanner to capture a patient's maxillary, mandibular gum shapes to generate stereoscopic maxillary, mandibular gum data and an occlusion record of a patient's maxilla and mandible; using a computer tomography scanner to scan patient's maxilla, mandible shapes to generate tomographic maxilla, mandible data; using a 3D processing device to consolidate the stereoscopic maxillary, mandibular gum data, occlusion record of a patient's maxilla and mandible, tomographic maxilla, mandible data to generate 3D full-tooth data; planning detailed positions and sizes of a upper (lower) prosthesis adapted to set on the patient maxilla (mandible) side, a plurality of upper (lower) fixing elements for fixing the upper (lower) prosthesis through the 3D full-tooth data; and making the upper, lower prostheses, and using each upper (lower) fixing element to implant the upper (lower) prosthesis into the patient's maxilla (mandible).

Abstract: A method includes forming a first gate, a second gate, a third gate, and a fourth gate over a substrate, in which a first distance between the first gate and the second gate is less than a second distance between the third gate and the fourth gate. A first spacer over a sidewall of the first gate, a second spacer over a sidewall of the second gate, a third spacer over a sidewall of the third gate, and a fourth spacer over a sidewall of the fourth gate are formed. A mask layer over the first and second spacers is formed, in which the third and fourth spacers are exposed from the mask layer. The exposed third and fourth spacers are trimmed.

Abstract: A semiconductor device includes a substrate; a first device disposed on the substrate, and the first device includes at least two first gate stacks, in which the two adjacent first gate stacks have a first distance therebetween; a plurality of first gate spacers having a first thickness disposed on opposite sidewalls of the first gate stacks; the semiconductor device further includes a second device disposed on the substrate, and the second device includes at least two second gate stacks, in which the two adjacent second gate stacks have a second distance therebetween, and the first distance is smaller than the second distance; a plurality of second gate spacers having a second thickness disposed on opposite sidewalls of the second gate stacks, and the first thickness is greater than the second thickness.

Abstract: A semiconductor device includes a substrate; a first device disposed on the substrate, and the first device includes at least two first gate stacks, in which the two adjacent first gate stacks have a first distance therebetween; a plurality of first gate spacers having a first thickness disposed on opposite sidewalls of the first gate stacks; the semiconductor device further includes a second device disposed on the substrate, and the second device includes at least two second gate stacks, in which the two adjacent second gate stacks have a second distance therebetween, and the first distance is smaller than the second distance; a plurality of second gate spacers having a second thickness disposed on opposite sidewalls of the second gate stacks, and the first thickness is greater than the second thickness.

Abstract: A digital visual interface dual-stack connector includes a holder base and a first connector and a second connector mounted in the holder base at different elevations, the second connector having multiple second terminal pins arranged in three sets and mounted in a slotted mating body portion of a housing thereof, each second terminal pin defining a vertical rear bonding portion, a horizontal front contact portion, an oblique support arm portion and two curved portions respectively connected between the vertical rear bonding portion and horizontal front contact portion and the two ends of the support arm portion. By means of controlling the bending angles of the two curved portions of the second terminal pins and the pitch between each two adjacent second terminal pins, the invention accurately achieves impedance matching to reduce high frequency signal reflection, enhancing signal transmission stability and reliability.

Abstract: A digital visual interface dual-stack connector includes a holder base and a first connector and a second connector mounted in the holder base at different elevations, the second connector having multiple second terminal pins arranged in three sets and mounted in a slotted mating body portion of a housing thereof, each second terminal pin defining a vertical rear bonding portion, a horizontal front contact portion, an oblique support arm portion and two curved portions respectively connected between the vertical rear bonding portion and horizontal front contact portion and the two ends of the support arm portion. By means of controlling the bending angles of the two curved portions of the second terminal pins and the pitch between each two adjacent second terminal pins, the invention accurately achieves impedance matching to reduce high frequency signal reflection, enhancing signal transmission stability and reliability.

Abstract: The present invention relates to an improved electrical connector adapted to transmit high-definition (HD) digital images. The improved electrical connector comprises a body, a first terminal assembly, a second terminal assembly, a first terminal connecting device, a second terminal connecting device, a first housing and a second housing. The first terminal assembly and the second terminal assembly are adapted to transmit signals, and by using the first housing and the second housing to cover the first terminal assembly and the second terminal assembly simultaneously, the problem of electromagnetic interference (EMI) suffered by the first terminal assembly and the second terminal assembly during high-frequency transmission is obviated, thereby improving the electromagnetic disturbance susceptibility thereof.

Abstract: The present invention relates to an improved electrical connector adapted to transmit high-definition (HD) digital images. The improved electrical connector comprises a body, a first terminal assembly, a second terminal assembly, a first terminal connecting device, a second terminal connecting device, a first housing and a second housing. The first terminal assembly and the second terminal assembly are adapted to transmit signals, and by using the first housing and the second housing to cover the first terminal assembly and the second terminal assembly simultaneously, the problem of electromagnetic interference (EMI) suffered by the first terminal assembly and the second terminal assembly during high-frequency transmission is obviated, thereby improving the electromagnetic disturbance susceptibility thereof.