Patents by Inventor Chung-Ping Chao

Chung-Ping Chao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050127427
    Abstract: Method and structure to improve the gate coupling ratio (GCR) for manufacturing a flash memory device are provided. The method and structure include the following steps. A gate oxide layer, a first semiconductor layer, and an insulating layer are formed sequentially over a provided semiconductor substrate. An etching process is used to etch the insulating layer. A semiconductor spacer is then deposited and used as a self-aligned etching mask. After the self-aligned etching, the insulating layer is removed and an insulating stacked structure is deposited. Finally, a second semiconductor layer is deposited and etched to form the control gate region.
    Type: Application
    Filed: November 15, 2004
    Publication date: June 16, 2005
    Inventors: Wen-Fang Lee, Wei-Lun Hsu, Chung-Ping Chao, Yu-Hsien Lin
  • Patent number: 6897116
    Abstract: Method and structure to improve the gate coupling ratio (GCR) for manufacturing a flash memory device are provided. The method and structure include the following steps. A gate oxide layer, a first semiconductor layer, and an insulating layer are formed sequentially over a provided semiconductor substrate. An etching process is used to etch the insulating layer. A semiconductor spacer is then deposited and used as a self-aligned etching mask. After the self-aligned etching, the insulating layer is removed and an insulating stacked structure is deposited. Finally, a second semiconductor layer is deposited and etched to form the control gate region.
    Type: Grant
    Filed: September 12, 2003
    Date of Patent: May 24, 2005
    Assignee: United Microelectronics Corp.
    Inventors: Wen-Fang Lee, Wei-Lun Hsu, Chung-Ping Chao, Yu-Hsien Lin
  • Publication number: 20050056879
    Abstract: Method and structure to improve the gate coupling ratio (GCR) for manufacturing a flash memory device are provided. The method and structure include the following steps. A gate oxide layer, a first semiconductor layer, and an insulating layer are formed sequentially over a provided semiconductor substrate. An etching process is used to etch the insulating layer. A semiconductor spacer is then deposited and used as a self-aligned etching mask. After the self-aligned etching, the insulating layer is removed and an insulating stacked structure is deposited. Finally, a second semiconductor layer is deposited and etched to form the control gate region.
    Type: Application
    Filed: September 12, 2003
    Publication date: March 17, 2005
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Fang Lee, Wei-Lun Hsu, Chung-Ping Chao, Yu-Hsien Lin
  • Patent number: 6443648
    Abstract: A ballpoint pen has an ink reservoir tube which stores ink, a point assembly disposed in the front of the ink reservoir tube, and a ball bearing held at the front end of the point assembly. The ball bearing is a shape memory alloy, preferably a TiNi intermetallic compound or a TiNi based alloy. The ball bearing solves the problem of ink failing to flow when the ballpoint pen is dropped on the ground.
    Type: Grant
    Filed: October 4, 2001
    Date of Patent: September 3, 2002
    Inventor: Chung Ping Chao