Patents by Inventor Chung Ping-Chung
Chung Ping-Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8850448Abstract: A dynamic reconfigurable heterogeneous processor architecture with load balancing and dynamic allocation method thereof is disclosed. The present invention uses a work control logic unit to detect load imbalance between different types of processors, and employs a number of dynamic reconfigurable heterogeneous processors to offload the heavier loaded processors. Hardware utilization of such design can be enhanced, and variation in computation needs among different computation phases can be better handled. To design the dynamic reconfigurable heterogeneous processors, a method of how to choose the basic building blocks and place the routing components is included. With the present invention, performance can be maximized at a minimal hardware cost. Hence the dynamic reconfigurable heterogeneous processor(s) so constructed and the load balancing and dynamic allocation method together will have the best performance at least cost.Type: GrantFiled: February 5, 2014Date of Patent: September 30, 2014Assignee: National Chiao Tung UniversityInventors: Chung-Ping Chung, Hui-Chin Yang, Yi-Chi Chen
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Publication number: 20140157285Abstract: A dynamic reconfigurable heterogeneous processor architecture with load balancing and dynamic allocation method thereof is disclosed. The present invention uses a work control logic unit to detect load imbalance between different types of processors, and employs a number of dynamic reconfigurable heterogeneous processors to offload the heavier loaded processors. Hardware utilization of such design can be enhanced, and variation in computation needs among different computation phases can be better handled. To design the dynamic reconfigurable heterogeneous processors, a method of how to choose the basic building blocks and place the routing components is included. With the present invention, performance can be maximized at a minimal hardware cost. Hence the dynamic reconfigurable heterogeneous processor(s) so constructed and the load balancing and dynamic allocation method together will have the best performance at least cost.Type: ApplicationFiled: February 5, 2014Publication date: June 5, 2014Applicant: National Chiao Tung UniversityInventors: Chung-Ping CHUNG, Hui-Chin YANG, Yi-Chi CHEN
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Patent number: 8656103Abstract: A processor and a method for executing load operation and store operation thereof are provided. The processor includes a data cache and a store buffer. When executing a store operation, if the address of the store operation is the same as the address of an existing entry in the store buffer, the data of the store operation is merged into the existing entry. When executing a load operation, if there is a memory dependency between an existing entry in the store buffer and the load operation, and the existing entry includes the complete data required by the load operation, the complete data is provided by the existing entry alone. If the existing entry does not include the complete data, the complete data is generated by assembling the existing entry and a corresponding entry in the data cache.Type: GrantFiled: July 20, 2012Date of Patent: February 18, 2014Assignee: Faraday Technology Corp.Inventors: Hui-Chin Yang, Shun-Chieh Chang, Guan-Ying Chiou, Chung-Ping Chung
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Publication number: 20120290791Abstract: A processor and a method for executing load operation and store operation thereof are provided. The processor includes a data cache and a store buffer. When executing a store operation, if the address of the store operation is the same as the address of an existing entry in the store buffer, the data of the store operation is merged into the existing entry. When executing a load operation, if there is a memory dependency between an existing entry in the store buffer and the load operation, and the existing entry includes the complete data required by the load operation, the complete data is provided by the existing entry alone. If the existing entry does not include the complete data, the complete data is generated by assembling the existing entry and a corresponding entry in the data cache.Type: ApplicationFiled: July 20, 2012Publication date: November 15, 2012Applicant: FARADAY TECHNOLOGY CORP.Inventors: Hui-Chin Yang, Shun-Chieh Chang, Guan-Ying Chiou, Chung-Ping Chung
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Patent number: 8078851Abstract: A method for recovering global history shift register (GHSR) and return address stack (RAS) is provided, which is applicable to an instruction pipeline of a processor and includes the following steps. First, provide a branch recovery table (BRT) and a backup stack. Whenever a branch instruction enters a predetermined stage of the instruction pipeline, add a record in the BRT according to the branch instruction. Whenever a return address is popped from the RAS of the instruction pipeline, push the return address into the backup stack. When flushing the instruction pipeline, determine a removal range of the BRT according to the condition which triggers the pipeline flush. Recover the RAS according to the records in the removal range and the backup stack. Remove all records in the removal range. Recover the GHSR of the instruction pipeline according to the removed records.Type: GrantFiled: December 18, 2008Date of Patent: December 13, 2011Assignee: Faraday Technology Corp.Inventors: Guan-Ying Chiou, Yuan-Jung Kuo, Hui-Chin Yang, Tzu-Min Chou, Shun-Chieh Chang, Chung-Ping Chung
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Publication number: 20110197048Abstract: A dynamic reconfigurable heterogeneous processor architecture with load balancing and dynamic allocation method thereof is disclosed. The present invention uses a work control logic unit to detect load imbalance between different types of processors, and employs a number of dynamically reconfigurable heterogeneous processors to offload the heavier loaded processors. Hardware utilization of such design can be enhanced, and variation in computation needs among different computation phases can be better handled. To design the dynamic reconfigurable heterogeneous processors, a method of how to choose the basic building blocks and place the routing components is included. With the present invention, performance can be maximized at a minimal hardware cost. Hence the dynamic reconfigurable heterogeneous processor(s) so constructed and the load balancing and dynamic allocation method together will have the best performance at least cost.Type: ApplicationFiled: February 3, 2011Publication date: August 11, 2011Inventors: Chung-Ping CHUNG, Hui-Chin Yang, Yi-Chi Chen
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Publication number: 20100250850Abstract: A processor and a method for executing load operation and store operation thereof are provided. The processor includes a data cache and a store buffer. When executing a store operation, if the address of the store operation is the same as the address of an existing entry in the store buffer, the data of the store operation is merged into the existing entry. When executing a load operation, if there is a memory dependency between an existing entry in the store buffer and the load operation, and the existing entry includes the complete data required by the load operation, the complete data is provided by the existing entry alone. If the existing entry does not include the complete data, the complete data is generated by assembling the existing entry and a corresponding entry in the data cache.Type: ApplicationFiled: March 25, 2009Publication date: September 30, 2010Applicant: FARADAY TECHNOLOGY CORP.Inventors: Hui-Chin Yang, Shun-Chieh Chang, Guan-Ying Chiou, Chung-Ping Chung
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Publication number: 20100161951Abstract: A method for recovering global history shift register (GHSR) and return address stack (RAS) is provided, which is applicable to an instruction pipeline of a processor and includes the following steps. First, provide a branch recovery table (BRT) and a backup stack. Whenever a branch instruction enters a predetermined stage of the instruction pipeline, add a record in the BRT according to the branch instruction. Whenever a return address is popped from the RAS of the instruction pipeline, push the return address into the backup stack. When flushing the instruction pipeline, determine a removal range of the BRT according to the condition which triggers the pipeline flush. Recover the RAS according to the records in the removal range and the backup stack. Remove all records in the removal range. Recover the GHSR of the instruction pipeline according to the removed records.Type: ApplicationFiled: December 18, 2008Publication date: June 24, 2010Applicant: FARADAY TECHNOLOGY CORP.Inventors: Guan-Ying Chiou, Yuan-Jung Kuo, Hui-Chin Yang, Tzu-Min Chou, Shun-Chieh Chang, Chung-Ping Chung
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Publication number: 20100049947Abstract: A processor and an early-load method thereof are provided. In the early-load method, an instruction is fetched and determined in an instruction fetch stage to obtain a determination result. Whether to early-load an early-loaded data corresponding to the instruction is determined according to the determination result. A target data is fetched according to the instruction in an instruction execution stage if the early-loaded data is not loaded correctly. The early-loaded data is served as the target data if the early-loaded data is loaded correctly.Type: ApplicationFiled: August 22, 2008Publication date: February 25, 2010Applicant: FARADAY TECHNOLOGY CORP.Inventors: Shun-Chieh Chang, Yuan-Hwa Li, Yuan-Jung Kuo, Chin-Ling Huang, Chung-Ping Chung
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Patent number: 7609180Abstract: A method and an apparatus for bus encoding and a method and an apparatus for bus decoding are provided. The methods and apparatuses for bus encoding/decoding use a discontinuous pattern table (DPT) to store discontinuous pattern pairs. The tables are kept synchronous in both transmitter and receiver ends. After transmitting the first data in a discontinuous pattern pair, the second data may be transmitted by merely informing the receiver end through a control line instead of transmitting the second data by the bus.Type: GrantFiled: September 29, 2007Date of Patent: October 27, 2009Assignee: Industrial Technology Research InstituteInventors: Tsung-Hsi Weng, Wei-Hau Chiao, Chung-Ping Chung, Chih-Wei Hsu, Yeu-Horng Shiau
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Publication number: 20090160870Abstract: The present invention discloses a texture filtering system, comprising a sequence generator, a retrieve unit and a dispatch unit. The sequence generator generates an execution sequence in each duty cycle. The execution sequence is the priority of respectively retrieving multiple pixels from multiple queues. The retrieve unit outputs multiple Boolean signals based on the limitation of the total number of all-purpose texture filters and the above priority in a duty cycle for determining from which queues the pixels are retrieved to perform a texture filtering process, and the dispatch unit assigns the multiple texture filter formats of the pixels to be processed and the anisotropic ratios thereof to multiple address generators.Type: ApplicationFiled: December 12, 2008Publication date: June 25, 2009Inventors: Wei-Ting WANG, Hui-Chin YANG, R-Ming HSU, Chung-Ping CHUNG
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Publication number: 20080235417Abstract: A method and an apparatus for bus encoding and a method and an apparatus for bus decoding are provided. The methods and apparatuses for bus encoding/decoding use a discontinuous pattern table (DPT) to store discontinuous pattern pairs. The tables are kept synchronous in both transmitter and receiver ends. After transmitting the first data in a discontinuous pattern pair, the second data may be transmitted by merely informing the receiver end through a control line instead of transmitting the second data by the bus.Type: ApplicationFiled: September 29, 2007Publication date: September 25, 2008Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Tsung-Hsi Weng, Wei-Hau Chiao, Chung-Ping Chung, Chih-Wei Hsu, Yeu-Horng Shiau
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Publication number: 20070130450Abstract: A system and method for unnecessary dynamic branch prediction elimination in a processor with a dynamic branch predictor, includes a branch distance generation module for generating a branch distance between two consecutive branch instructions, a branch distance table for storing the branch distance generated by the branch distance generation module, and a dynamic branch predictor enabling module for determining enable or disable the dynamic branch prediction by using the branch distances stored in the branch distance table for the next incoming instructions. Through the configuration of the system, the dynamic branch prediction is performed only for branch instruction, so as to save power consumption due to unnecessary dynamic branch predictions.Type: ApplicationFiled: June 12, 2006Publication date: June 7, 2007Inventors: Wei-Hau Chiao, Yau-Chong Hu, Chung-Ping Chung, Jean Shann, Chia-Wen Cheng
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Patent number: 6301651Abstract: The present invention provides a stack machine for executing a plurality of instructions one by one. The stack machine comprises an operation folder and an execution unit. The operation folder is used for checking if one or more instructions of a predetermined number of instructions following a specific instruction in a predetermined sequence can be folded with the specific instruction according to a POC folding rule. If they are foldable, these instructions will be combined to form a new instruction. The execution unit is used for executing instructions which cannot be folded by the operation folder or new instructions generated by the operation folder one by one. The instructions are folded to enhance operation efficiency of the stack machine.Type: GrantFiled: June 28, 1999Date of Patent: October 9, 2001Assignee: Industrial Technology Research InstituteInventors: Lung-Chung Chang, Lee-Ren Ton, Min-Fu Kao, Chung-Ping Chung
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Patent number: 6187080Abstract: An exhaust gas treatment apparatus for treating exhaust gas generated in semiconductor manufacturing processes. It includes a main pipe, a gas vortex means, a water vortex means, an U pipe and a discharge pipe. The main pipe transforms the exhaust gases to waste powder which are discharged out through the U pipe and the discharge pipe. The gas vortex means and water vortex means are located below the main pipe for generating annular and even downward gas flow and water flow at the outlet of the main pipe for preventing reflux of waste powder from entering into the main pipe. Waste powder thus won't deposit around the outlet. Scraper in the main pipe won't be stuck or deformed. Waste powder may be discharged out through the U pipe and discharge pipe smoothly and efficiently.Type: GrantFiled: August 9, 1999Date of Patent: February 13, 2001Assignee: United Microelectronics Inc.Inventors: Chung Ping-Chung, Lu Tsung-Lin, Chi-Hsien Chen, Jing-Yi Huang, Ju-Long Lee, Hunter Chung, Chien-Feng Chen
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Patent number: 6115686Abstract: A system for converting a hyper text markup language (HTML) document to speech includes an HTML parser, an HTML to speech (HTS) control parser, a tag converter, a text normalizer and a TTS converter. The HTML parser receives data of an HTML formatted document and parses out content text, HTML text tags that structure the content text and control rules used only for translating the received data into sound. The HTS control parser parses control rules for converting the received data into sound. The HTS control parser modifies entries in one or more of a tag mapping table, an audio data table, a parameter set table, an enunciation modification table and a terminology translation table depending on each of the parsed control rules. The text normalizer modifies enunciation of each text string of the content text of the HTML document for which the enunciation modification table has an entry, according to an enunciation modification indicated in the respective enunciation table entry.Type: GrantFiled: April 2, 1998Date of Patent: September 5, 2000Assignee: Industrial Technology Research InstituteInventors: Jin-Chin Chung, Shaw-Hwa Hwang, Chung-Ping Chung
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Patent number: 6101552Abstract: A virtual internet protocol (IP) gate, between a legitimate internet and a virtual internet, can reuse the internet address in a specific range of the legitimate internet addresses for resolving the insufficiency of IP addressing. The virtual IP gate at least comprises a connection module, a selection module and an address conversion module. The connection module establishes connection with the virtual internet by using at least a virtual internet address and establishes connection with the internet by using at least an internet address with the address not within the aforementioned range.Type: GrantFiled: October 6, 1998Date of Patent: August 8, 2000Inventors: Yen-Yuan Chiang, Hsiao-Ping Tsai, Chung-Ping Chung