Patents by Inventor Chung-Ping Eng
Chung-Ping Eng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090094567Abstract: Method embodiments herein determine a connection order in which connections will be made to connect active devices to antennas within a given circuit design. The method also evaluates the possibilities that these connections to the antennas will cause charging damage in the devices that are connected to the antennas. Such possibilities are based on the connection order, the size of the antennas, and the likelihood that charges will flow from the antennas through insulators of the devices. If a significant possibility for damage exists, the method can reduce the size of the antenna.Type: ApplicationFiled: October 9, 2007Publication date: April 9, 2009Inventors: Chung-Ping Eng, Terence B. Hook, Jeffrey S. Zimmerman
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Patent number: 7372158Abstract: A cap nitride stack which prevents etch penetration to the HDP nitride while maintaining the electromigration benefits of HDP nitride atop Cu. In one embodiment, the stack comprises a first layer of HDP nitride and a second layer of a Si—C—H compound disposed over the first layer. The Si—C—H compound is for example BLoK, or N-BLoK (Si—C—H—N), and is selected from a group of materials that has high selectivity during via RIE such that RIE chemistry from the next wiring level does not punch through. Carbon and nitrogen are the key elements. In another embodiment, the stack comprises a first layer of HDP nitride, followed by a second layer of UVN (a plasma nitride), and a third layer comprising HDP nitride disposed over the second layer.Type: GrantFiled: August 28, 2006Date of Patent: May 13, 2008Assignee: International Business Machines CorporationInventors: Yun-Yu Wang, Richard A Conti, Chung-Ping Eng, Matthew C Nicholls
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Publication number: 20070271540Abstract: Disclosed is a protection circuit for an integrated circuit device, wherein said protection circuit comprises: a first element connected to a gate of a first FET device; and a second element connected to a gate of a second FET device, wherein a drain/source of the first FET device and a drain/source of the second FET device are connected to a higher level connector and wherein the higher level connector eliminates a damaging current path between the first element and the second element.Type: ApplicationFiled: May 16, 2006Publication date: November 22, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chung-Ping Eng, Henry A. Bonges, Jeffrey S. Zimmerman, Terence B. Hook
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Publication number: 20070004206Abstract: A cap nitride stack which prevents etch penetration to the HDP nitride while maintaining the electromigration benefits of HDP nitride atop Cu. In one embodiment, the stack comprises a first layer of HDP nitride and a second layer of a Si—C—H compound disposed over the first layer. The Si—C—H compound is for example BLoK, or N-BLoK (Si—C—H—N), and is selected from a group of materials that has high selectivity during via RIE such that RIE chemistry from the next wiring level does not punch through. Carbon and nitrogen are the key elements. In another embodiment, the stack comprises a first layer of HDP nitride, followed by a second layer of UVN (a plasma nitride), and a third layer comprising HDP nitride disposed over the second layer.Type: ApplicationFiled: August 28, 2006Publication date: January 4, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yun-Yu Wang, Richard Conti, Chung-Ping Eng, Matthew Nicholls
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Patent number: 7138717Abstract: A cap nitride stack which prevents etch penetration to the HDP nitride while maintaining the electromigration benefits of HDP nitride atop Cu. In one embodiment, the stack comprises a first layer of HDP nitride and a second layer of a Si—C—H compound disposed over the first layer. The Si—C—H compound is for example BLoK, or N-BLoK (Si—C—H—N), and is selected from a group of materials that has high selectivity during via RIE such that RIE chemistry from the next wiring level does not punch through. Carbon and nitrogen are the key elements. In another embodiment, the stack comprises a first layer of HDP nitride, followed by a second layer of UVN (a plasma nitride), and a third layer comprising HDP nitride disposed over the second layer.Type: GrantFiled: December 1, 2004Date of Patent: November 21, 2006Assignee: International Business Machines CorporationInventors: Yun-Yu Wang, Richard A. Conti, Chung-Ping Eng, Matthew C. Nicholls
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Publication number: 20060113672Abstract: A cap nitride stack which prevents etch penetration to the HDP nitride while maintaining the electromigration benefits of HDP nitride atop Cu. In one embodiment, the stack comprises a first layer of HDP nitride and a second layer of a Si—C—H compound disposed over the first layer. The Si—C—H compound is for example BLoK, or N-BLoK (Si—C—H—N), and is selected from a group of materials that has high selectivity during via RIE such that RIE chemistry from the next wiring level does not punch through. Carbon and nitrogen are the key elements. In another embodiment, the stack comprises a first layer of HDP nitride, followed by a second layer of UVN (a plasma nitride), and a third layer comprising HDP nitride disposed over the second layer.Type: ApplicationFiled: December 1, 2004Publication date: June 1, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yun-Yu Wang, Richard Conti, Chung-Ping Eng, Matthew Nicholls
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Patent number: 7008803Abstract: Methods of etching a semiconductor structure using ion milling with a variable-position endpoint detector to unlayer multiple interconnect layers, including low-k dielectric films. The ion milling process is controlled for each material type to maintain a planar surface with minimal damage to the exposed materials. In so doing, an ion beam mills a first layer and detects an endpoint thereof using an optical detector positioned within the ion beam adjacent the first layer to expose a second layer of low-k dielectric film. Once the low-k dielectric film is exposed, a portion of the low-k dielectric film may be removed to provide spaces therein, which are backfilled with a material and polished to remove the backfill material and a layer of the multiple interconnect metal layers. Still further, the exposed low-k dielectric film may then be removed, and the exposed metal vias polished.Type: GrantFiled: October 24, 2002Date of Patent: March 7, 2006Assignee: International Business Machines CorporationInventors: Terence Lawrence Kane, Chung-Ping Eng, Brett H. Engel, Barry Jack Ginsberg, Dermott A. Macpherson, John Charles Petrus
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Publication number: 20050285106Abstract: Methods of etching a semiconductor structure using ion milling with a variable-position endpoint detector to unlayer multiple interconnect layers, including low-k dielectric films. The ion milling process is controlled for each material type to maintain a planar surface with minimal damage to the exposed materials. In so doing, an ion beam mills a first layer and detects an endpoint thereof using an optical detector positioned within the ion beam adjacent the first layer to expose a second layer of low-k dielectric film. Once the low-k dielectric film is exposed, a portion of the low-k dielectric film may be removed to provide spaces therein, which are backfilled with a material and polished to remove the backfill material and a layer of the multiple interconnect metal layers. Still further, the exposed low-k dielectric film may then be removed, and the exposed metal vias polished.Type: ApplicationFiled: August 17, 2005Publication date: December 29, 2005Inventors: Terence Kane, Chung-Ping Eng, Brett Engel, Barry Ginsberg, Dermott MacPherson, John Petrus
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Publication number: 20040082176Abstract: Low-k dielectric films such as SiLK are desirably used in semiconductor structures, for example in back-end multilevel metal interconnect structures, as insulators. Low-k dielectric films, however, are prone to damage in the course of typical rework processes such as chemical-mechanical polishing, plasma/reactive ion etching, or wet chemistry processing/etching. The present invention uses an ion milling process with a variable-position endpoint detector to unlayer multiple layers including low-k dielectric films. The ion milling process can be controlled for each material type so as to maintain a planar surface with minimal or no damage to the exposed materials.Type: ApplicationFiled: October 24, 2002Publication date: April 29, 2004Applicant: Intenational Business Machines CorporationInventors: Terence Lawrence Kane, Chung-Ping Eng, Brett H. Engel, Barry Jack Ginsberg, Dermott A. Macpherson, John Charles Petrus
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Patent number: 6436823Abstract: A method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure without the formation of a thick amorphous layer containing Ti, Co and Si and the structure formed are provided. In the method, after a Ti layer is deposited on top of a metal silidide layer, a dual-step annealing process is conducted in which a low temperature annealing in a forming gas (or ammonia) at a temperature not higher than 500° C. is first conducted for less than 2 hours followed by a high temperature annealing in a nitrogen-containing gas (or ammonia) at a second temperature not lower than 500° for less than 2 hours to form the TiN layer. The present invention method prevents the problem usually caused by a thick amorphous material layer of Ti—Si—Co which produces weakly bonded Ti which reacts with fluorine atoms from WF6 during a subsequent CVD W deposition process and causes liner failure due to a volume expansion of the amorphous material.Type: GrantFiled: October 5, 2000Date of Patent: August 20, 2002Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Chung-Ping Eng, Lynne Marie Gignac, Christian Lavoie, Patricia O'Neil, Kirk David Peterson, Tina Wagner, Yun-Yu Wang, Keith Wong
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Patent number: 6387790Abstract: A method of fabricating a Ti-containing liner having good contact resistance and coverage of a contact hole is provided. The method which converts an amorphous region of ionized metal plasma deposited Ti into a substantially crystalline region includes (a) providing a structure having at least one contact hole formed therein, said at least one contact hole exposing at least a portion of a cobalt disilicide contact formed in a semiconductor substrate; (b) depositing a Ti/TiN liner in said at least one contact hole by ionized metal plasma deposition; (c) annealing said Ti/TiN liner under conditions effective to recrystallize any amorphous region formed during said annealing into a crystalline region including a TiSi2 top layer and a CoSix bottom layer; and (d) optionally forming a conductive material on said Ti/TiN liner.Type: GrantFiled: June 23, 2000Date of Patent: May 14, 2002Assignee: International Business Machines CorporationInventors: Anthony Gene Domenicucci, Chung-Ping Eng, William Joseph Murphy, Tina J. Wagner, Yun-Yu Wang, Kwong Hon Wong