Patents by Inventor Chung-Ping Hsia

Chung-Ping Hsia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240387395
    Abstract: A semiconductor device, a method of forming the same and a method of measuring the same are disclosed. The semiconductor device includes a substrate, a first dielectric layer, first alignment marks, a second dielectric layer and second alignment marks. The first dielectric layer is arranged on the substrate, the first alignment marks are arranged in the first dielectric layer. The second dielectric layer is disposed on the first dielectric layer. The second alignment marks are arranged in the second dielectric layer and spaced apart from each other, each having a stepped structure. The first and second alignment marks do not interfere with each other. A precisely positioned interconnection structure can thus be defined in the semiconductor device.
    Type: Application
    Filed: September 5, 2023
    Publication date: November 21, 2024
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: JIANPENG LAI, Rongxiang Zhong, Yue Liu, Chung-Ping Hsia
  • Publication number: 20240334674
    Abstract: A semiconductor device and a method of forming the same are disclosed. The semiconductor device includes a substrate, a plurality of active areas, a shallow trench isolation and a plurality of buried gates. The active areas are formed on the substrate, wherein each active area includes a semiconductor layer, and a first interface exists between the semiconductor layer and the substrate. The shallow trench isolation is disposed on the substrate and surrounds the active areas. Each buried gates is buried in one of the plurality of active areas and disposed above the first interface. Accordingly, the isolation effect between the active areas can be enhanced on the condition of maintaining a certain level of integration. Meanwhile, the possible device defects derived from the raised level of integration can be ameliorated.
    Type: Application
    Filed: July 28, 2023
    Publication date: October 3, 2024
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: GUANGRONG WANG, Feng-Lun Wu, Chung-Ping Hsia, MIAO SUN
  • Publication number: 20240057310
    Abstract: A semiconductor memory device includes a substrate, and a plurality of contact pads and a capacitor array structure disposed on an array region of the substrate. The capacitor array structure includes a plurality of capacitors respectively disposed on the contact pads and a middle supporting layer extending laterally between waist portions of the capacitors to define an upper portion and a lower portion of each of the capacitors. The lower portions of the capacitors near the edge of the array region are tilted. The upper portions of the capacitors near the edge of the array region have misalignments to the contact pads. The stress in the capacitor array structure of the semiconductor memory device may be reduced.
    Type: Application
    Filed: December 26, 2022
    Publication date: February 15, 2024
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yincong Hong, Chia-Hung Wang, Yue Liu, Chung-Ping Hsia
  • Patent number: 10276395
    Abstract: The present invention provides a method for manufacturing a semiconductor device including following steps. A substrate, a hard mask layer disposed on the substrate and a first mask pattern disposed on the hard mask layer are provided, and the substrate has a device region and a cutting line region. The first mask pattern has first gaps in the device region and second gaps in the cutting line region. Next, a spacer layer conformally covers the first mask pattern. Then, a second mask pattern is formed on the spacer layer in the first gaps, and a top surface of the second mask pattern is lower than a top surface of the first mask pattern. Thereafter, an etching process is performed to the spacer layer to remove the spacer layer between the first mask layer and the second mask layer and in the second gaps and expose the hard mask layer.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: April 30, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chien-Hao Chen, Feng-Lun Wu, Chung-Ping Hsia, Sho-Shen Lee
  • Publication number: 20180286692
    Abstract: The present invention provides a method for manufacturing a semiconductor device including following steps. A substrate, a hard mask layer disposed on the substrate and a first mask pattern disposed on the hard mask layer are provided, and the substrate has a device region and a cutting line region. The first mask pattern has first gaps in the device region and second gaps in the cutting line region. Next, a spacer layer conformally covers the first mask pattern. Then, a second mask pattern is formed on the spacer layer in the first gaps, and a top surface of the second mask pattern is lower than a top surface of the first mask pattern. Thereafter, an etching process is performed to the spacer layer to remove the spacer layer between the first mask layer and the second mask layer and in the second gaps and expose the hard mask layer.
    Type: Application
    Filed: March 21, 2018
    Publication date: October 4, 2018
    Inventors: Chien-Hao Chen, Feng-Lun Wu, Chung-Ping Hsia, Sho-Shen Lee